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无与伦比的灵活性和特性,不影响性价比或功耗。

在开放式协作服务爆炸性增长以及移动和社交网络不断发展的推动下,结合智能设备的普及以及不同服务供应商和企业领域内体验质量 (QoE) 需求一致化的大趋势,动态托管数据包处理的需求正在不断快速发展。

Xilinx 推出了各种丰富的 Smarter Solution,将流量控制、优先级和监控功能扩展到单个数据包、会话或应用的粒度级上。这些解决方案支持网络设备检查和操控数据包报头和负载内容,并动态应用高级路由策略。此外,这些 Xilinx Smarter Solution 还能与安全、加密和 RegEx 功能方便集成。

面向数据包处理的 Xilinx Smarter Solution 包括All Programmable FPGA3D ICSoC以及一系列 SmartCORE IP,可进行定制优化以满足独特的市场需求。Xilinx Vivado™设计套件通信设计中心能以更快速灵活的方法向市场推出更具差异化的产品,并相对于 ASIC 和 ASSP 解决方案而言降低风险和总拥有成本。

Xilinx 数据包产品组合支持的示例应用包括核心路由/开关、软件定义网络、新一代路由和“Quad-Play Plus”服务等。如您有任何具体需求,敬请咨询 Xilinx 销售代表。

适用于包处理的 Xilinx 智能解决方案包括:

  • 层级流量管理器提供高度参数化的特性,能针对具体域的配置进行调节。
  • Flexible interface options:1Gbps/10Gbps/40Gbps/100Gbps/Interlaken allow customer proprietary I/F
  • Flexible CPU interface options: Ethernet and PCIe® allow customer proprietary I/F
  • Supports minimum Ethernet packet size (at full line-rate) and jumbo frames
  • Permits significant value differentiation via integration of customer-specific configuration “know-how” and proprietary blocks via custom integration by Xilinx Communication Design Center
  • 统一架构,可在 10Gbps 到100Gbps(将来可实现 200Gbps)带宽间以及 2K 到 64k 队列间扩展,可通过标准 API 对所有功能进行动态编程
  • User-transparent data base management with advanced memory packing
  • Optimal memory utilization to address specific instantiation and data base structures
    • 在内部 BRAM 中全面支持低带宽和低队列计数配置。
    • 高带宽/高数量的队列采用 BRAM 和[FPGA]业界最高 I/O 带宽的组合,支持高密度存储器配置:
      • DDR3 @ 1866Mbps、RLDRRAM3 @ 800MHz、和QDRII+ @ 500MHz
  • Scalable architecture enabling up to 5 levels of scheduling hierarchy, where each level could be independently configured with policing, shaping, scheduling and congestion/flow control features
  • Full support for broadcast and multicast
  • Congestion control: TD, RED, and WRED
  • 流量控制 - 按照队列/按照队列的聚集/按照层级等级
  • Scheduling: SP, Deficit Weighted Round Robin(DWRR), patent pending SP+ (for optimal combination of scheduling functions)
  • Policing: discard or marking based on srTCM, trTCM, and mefTCM
  • Statistics: per queue, per aggregate, per hierarchy covering all events
  • Extensive IP monitoring facility with interrupts and status accessible via APIs
  • Virtex®-7 FPGA 上的参考设计支持 32K 队列和三个层级,可为 Xilinx FAE 和架构师提供演示。
  • Major advances in network programming enabling rapid networking stack development
  • Intuitive declarative packet-oriented programming language speeds packet parsing including header and payload
  • Suite of advanced compilation tools enabling generation of RTL that is tuned to Xilinx FPGA architecture
  • Netlist generation guided by various parameters
    • Protocols
    • Packet formats
    • Compilation-time optimization parameters
      • FPGA family/device
      • Bus width
      • Clock frequency, etc.
  • Parser output processed by Xilinx FPGA tool chain (ISE® or Vivado Design Suites)
  • Parser can examine data streams of any length with fixed or variable space between sequential fields
  • Tool chain allows static implementation with fixed configurations for FPGA families/devices
  • Advanced options enable in-socket programmability (initial product rollout will require Xilinx customization service via CDC)
  • Extensive IP monitoring facility with interrupts and status accessible via APIs
  • Reference design on Virtex-7 device offering 5-tuple parsing examples available for demos by Xilinx FAE and architects

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