| Summary |
|
Xilinx provides two ways to evaluate the 3GPP Downlink Chip rate core: Simulation Only, and Full System
Hardware Evaluation.
- Simulation Only Evaluation allows
you to customize the core through a CORE Generator™
customization GUI and generate a Unisim-based model for
functional simulation.
- Full System Hardware Evaluation
allows you to do everything you can do with the Fully Licensed
IP core, including configure place and route, simulate,
estimate timing and program a Xilinx FPGA device.
|
| Requirements |
|
Install these updates if you have not already done so:
| Updates |
Installation Instructions and
Release Notes |
ISE™ 9.2i
IP Update 1
ISE 9.2i SP2 |
- Install the required updates in one of the following
ways:
- Run WebUpdate from the ISE Project Navigator
Help menu, or CORE Generator™ Tools
menu,
- Download the indicated updates from the
Xilinx Download
Center and run the standalone installer
- The required ISE Service Pack is automatically
installed with the selected IP Update when
using either method.
- Review the Critical Information link for
the IP Update on Download
Center for Installation instructions and
Release Note information on What's New, Bugs
Fixed and Known Issues.
|
(NOTE: You must be registered on Xilinx.com to access
these updates.)
|
| License Terms |
| Please note that the conditions of the
LogiCORE™
Evaluation License Agreement apply toward your evaluation
of this core. |
| Accessing
the Evaluation Files |
| Simulation
Only Evaluation |
|
To perform a Simulation Only Evaluation:
- Make sure you have installed the required software as
specified in the requirements section to ensure that you
have the required software and IP core version. The Simulation
Eval license key is shipped with the core by default.
- Follow the general instructions below on Generating
the Core.
- Integrate the core into your design and perform a functional
simulation.
|
| Full
System Hardware Evaluation |
|
To perform a Full System Hardware Evaluation:
- Make sure you have satisfied the requirements.
- Generate
a Full System Hardware Evaluation license Key.
- The license will be generated and emailed to you automatically.
Install the license as directed by the email instructions.
- Follow the general instructions below on Generating
the Core.
- To perform an in-depth evaluation in hardware in your
own design:
- Instantiate the core in your own design, place and route
the design using ISE, then generate a bitstream and use
it to program an appropriate FPGA device.
| Note that the core will cease to function in the programmed
device after 8 hours. |
|
| Generating
the Core |
- Start the CORE Generator using either of the following
methods:
- From ISE: Select Projects -> New Source
-> IP (Coregen and Architecture Wizard)
- From Windows: Select Programs -> Xilinx
-> Accessories -> CORE Generator
- The 3GPP Downlink Chip rate core is located in the Communication
and Networking/Wireless folder in the IP catalog section
of the CORE Generator window.
|
| Release Notes &
Known Issues |
|
Please review the Critical Information link for the
required IP Update on Download
Center for the latest version of the Release notes for
this core.
|
| Learn More |
You can learn more about the Xilinx 3GPP Downlink Chip Rate LogiCORE™ by visiting the 3GPP Downlink Chip Rate Core product page.
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