LogiCORE |
Version |
Software Support |
Required Patches |
Supported Device and Speed Grades |
|---|---|---|---|---|
Endpoint PIPE for PCI Express®
|
v1.7 | ISE® 9.1i SP3 IP Update 3 or higher Service Pack
|
Check the IP Release Notes Guide for information on any required patches. | Spartan®-3 (-4) Spartan-3E (-4) Spartan-3A (-4) |
Accessing the NXP PX1011A PHY Simulation Files |
|---|
A NXP PX1011A-EL1 PCI Express PHY model is required to simulate the Xilinx LogiCORE™ IP Endpoint PIPE for PCI Express (EF-DI-PCIE-PIPE-SITE). This PHY model is the property of NXP, and is not included with the Xilinx LogiCORE IP release. Please refer to the Getting Started Guide for information on accessing this model.
Be sure to include your complete contact information in any correspondence with NXP to facilitate a prompt response. |
Download the required software from the Xilinx.com Downloads page.
* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores in this table will be fully functional in the programmed device for approximately 8 hours. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again