Reed Solomon Decoder

ISE® 11.2

ISE IP Update 11.2
(IP_11.2)

Virtex®-6 LXT / SXT
Virtex-5 LX
Virtex-4 FX / SX / LX

Spartan®-6 LX / LXT
Spartan-3A / 3AN / 3A-DSP
Spartan-3E

ISE 9.1i

ISE 9.1i IP Update 3

Reed Solomon Encoder

ISE 11.2

ISE IP Update 11.2
(IP_11.2)

Virtex-6 LXT / SXT
Virtex-5 LX
Virtex-4 FX / SX / LX

Spartan-6 LX / LXT
Spartan-3A / 3AN / 3A-DSP
Spartan-3E

ISE 9.1i

ISE 9.1i IP Update 3

Hardware Evaluation Time Out Period

A Hardware Evaluation license for the Reed Solomon Decoder LogiCORE™ IP core will enable you to parameterize, generate and instantiate this cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.

The IP cores will be fully functional in the programmed device for approximately 2 - 3 hours. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again

Download the software requirements from the Software Updates page if you have not already done so.