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XILINX
Developer Forum 2017

Access Content

Tokyo

9:30AM - 6:00PM
October 17, 2017

Tokyo Marriott Hotel
4 Chome-7-36 Kitashinagawa, Shinagawa,
Tokyo 140-0001, Japan

Keynote Speaker: David Pellerin
Business Development Principal, HPC,
Amazon Web Services

This keynote will focus on FPGA development and deployment of cloud-scale applications, showing you how to get started, building cloud scale applications, commercialization and development tool updates.

With the availability of FPGAs on AWS, developers are creating custom hardware accelerated solutions to solve complex problems in areas like big data processing, healthcare and life sciences, security, image and video processing, financial and oil and gas applied research. Amazon EC2 F1 provides developers with a cloud development framework, ability to rapidly scale their accelerations, and enabling access to millions of AWS customers by offering AWS Marketplace.

Agenda for Xilinx Developer Forum Tokyo

Software Application Development

For software developers working on heterogeneous systems, looking to accelerate applications including machine learning, vision, video, and genomics using reconfigurable logic & massive parallelism

Registration & Breakfast

8:45am - 9:30am

Welcome & Introduction

9:30am - 9:40am

Xilinx Keynote

9:40am - 10:10am

Keynote Address: David Pellerin, Amazon

10:10am - 10:40am

Short Break to move to break out rooms

10:40am - 10:50am

An Introduction to reVISION & Reconfigurable Acceleration Stacks

10:50am - 11:20am

Speak to the Experts -- Interactive Break

11:20am - 11:50am

Xilinx Architecture and Solution for Deep Learning

11:50am - 12:20pm

Xilinx Open Source Application Libraries and Frameworks

12:20am - 12:50pm

Luch

12:50am - 1:40pm

SDx Development Environment: Compile, Debug & Profile in C/C++/OpenCL

1:40pm - 2:10pm

Short Break to move to break room

2:10pm - 2:20pm

reVISION Deep Dive: Computer Vision & Machine Learning

2:20pm - 3:20pm

Getting Started on AWS F1

2:20pm - 3:20pm

Deep learning with MPSoC based intelligent Camera module and implement ISP IP with using reVISION Stack -
Regulus

3:20pm - 3:50pm

AWS F1 Application Use Case -
Deephi Tech

3:20pm - 3:50pm

Short Break to move to break room

3:50pm - 4:20pm

DeepLearning implementation of using SDSoC development environment -
Konica Minolta

4:20pm - 5:05pm

Accelerating Enterprise Application in the Public Cloud

4:20pm - 5:05pm

Closing Remarks

5:05pm - 5:15pm

Networking Reception

5:15pm - 6:00pm

Embedded Software Development

For embedded software developers needing system software for multi-processor, heterogeneous, or reconfigurable systems on a single chip

Registration & Breakfast

8:45am - 9:30am

Welcome & Introduction

9:30am - 9:40am

Xilinx Keynote

9:40am - 10:10am

Keynote Address: David Pellerin, Amazon

10:10am - 10:40am

Short Break to move to break out rooms

10:40am - 10:50am

Heterogeneous SW Platforms

10:50am - 11:35am

Speak to the Experts -- Interactive Break

11:35am - 12:05pm

Xen from Cloud to Embedded

12:05pm - 12:50pm

Lunch

12:50pm - 1:50pm

eSOL Software Platform Technology Seamlessly Integrated with the Xilinx reVISION stack -
eSOL

1:50pm - 2:20pm

Yocto Enablement

2:20pm - 3:05pm

Develop & Debugging Heterogeneous Platforms

3:05pm - 3:50pm

Speak to the Experts -- Interactive Break

3:50pm - 4:20pm

Embedded Multimedia Systems

4:20pm - 5:05pm

Closing Remarks

5:05pm - 5:15pm

Networking Reception

5:15pm - 6:00pm

Hardware Development

For hardware developers using the Vivado Design Suite HLx Editions seeking to accelerate their productivity with best practices from industry experts

Registration & Breakfast

8:45am - 9:30am

Welcome & Introduction

9:30am - 9:40am

Xilinx Keynote

9:40am - 10:10am

Keynote Address: David Pellerin, Amazon

10:10am - 10:40am

Short Break to move to break out rooms

10:40am - 10:50am

Need for FPGA-based Platform Design

10:50am - 11:35am

Speak to the Experts -- Interactive Break

11:35am - 12:05pm

Leveraging Designer Assistance in IP Integrator

12:05am - 12:50pm

Lunch

12:50pm - 1:50pm

Verification Best Practices

1:50pm - 2:35pm

Advanced Synthesis Techniques

2:35pm - 3:20pm

Speak to the Experts -- Interactive Break

3:20pm - 3:50pm

Vivado Expert Panel Discussion

3:50pm - 4:20pm

Design Closure: Tips and Tricks

4:20pm - 5:05pm

Closing Remarks

5:05pm - 5:15pm

Networking Reception

5:15pm - 6:00pm

Venue: Tokyo Marriott Hotel

Address:
4 Chome-7-36 Kitashinagawa, Shinagawa,
Tokyo 140-0001, Japan

Tel:
03-5488-3911

For questions please click here.

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