Backplane

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Address the signal integrity challenges, high bandwidth per pin requirements and connectivity topologies of the backplane.

Xilinx provides pre-verified, drop-in intellectual property solutions for all major backplane standards, allowing you to focus on the value-added portion of the design. Use the following table to learn more about specific protocol solutions.

Backplane Protocols
Protocol	Line Rate	IP	Characterization Report	Compliance/ Interoperability	FPGA Family	Board	Market
XAUI	3.125 Gbps	Soft IP	Download	UNH IOL tested	Virtex™-5, Virtex-4 FX, Virtex-II Pro	Yes	Communications, networking, wireless, embedded
Gigabit Ethernet	1.25 Gbps	Hard block Soft IP	Download	UNH IOL tested	Virtex-5, Virtex-4 FX, Virtex-II Pro, Spartan™-3E	Yes	Communications, networking, wireless, embedded, servers, storage
PCI Express®	2.5 Gbps	Hard block Soft IP	Download	PCI-SIG® passed	Virtex-5, Virtex-4 FX, Virtex-II Pro, Spartan-3E	Yes, with kit	Servers, storage, communications, networking, wireless, embedded
SRIO	1.25 Gbps 2.5 Gbps 3.125 Gbps	Soft IP	Notify me	Testing pending	Virtex-5 LXT, Virtex-4 FX, Virtex-II Pro	Yes	Wireless, embedded
OBSAI	768 Mbps 1.536 Gbps 3.072 Gbps	Notify me	Notify me	Notify me	Virtex-5 LXT	No	Embedded
CPRI	614 Mbps 1.229 Gbps 2.458 Gbps	Notify me	Download	Characterization report	Virtex-5 LXT	No	Embedded

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