Chip-to-Chip

Address low latency and deterministic latency requirements and maintain very high reliability links from chip to chip.

Xilinx Virtex™-5 and Virtex-4 FPGAs include RocketIO™ multi-gigabit transceivers and high-speed differential I/O to reduce I/O power, costs, and complexity. They also provide high-performance capabilities and functions needed to connect chips at gigabit speeds. Use the following table to learn more about specific protocol solutions.

Chip-to-Chip Protocols
Protocol  Line Rate IP Characterization Report Compliance/ Interoperability FPGA Family Board Market
PCI Express® 2.5 Gbps
Hard block
Soft IP
Download PCI-SIG® passed Virtex-5, Virtex-4 FX, Virtex-II Pro, Spartan™-3E Yes, with kit Servers, storage, communications, networking, wireless, embedded
SRIO 1.25 Gbps
2.5 Gbps
3.125 Gbps
Soft IP Notify me Testing pending Virtex-5 LXT, Virtex-4 FX, Virtex-II Pro Yes Wireless, embedded
SPI/SFI <10 Gbps Soft IP Notify me Testing Pending Virtex-5, Virtex-4 Yes Communication
Aurora <3.2 Gbps Soft IP Notify me Testing Pending Virtex-5 LXT, Virtex-4 FX, Virtex-II Pro Yes All
CAN <1 Mbps Soft IP Notify me Testing Pending Virtex-4 FX/LX/SX, Virtex-II Pro, Spartan-3E/3A/3XA Yes Automotive
MOST® 23 Mbps Soft IP Notify me Testing Pending Virtex-4, Spartan-3 Yes Automotive
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