Aurora is released as a part of CORE Generator™ software, with a number of configurable parameters. It can be configured by selecting streaming/framing interface, simplex/full duplex data flow, single/multiple MGT’s, reference clock value, line rate, MGT location(s) based on number of MGTs selected, and reference clock source.

The Aurora protocol and its associated designs address the challenge of controlling and managing the MGT’s control interface. With Aurora, one or more MGT’s can be connected to form a communication channel. The Aurora protocol defines the structure of data packets and procedures for flow control, data striping, error handling, and initialization to validate MGT links. Aurora shrink-wraps MGT’s by providing a transparent interface.

The Aurora Protocol describes the transfer of user data across an Aurora channel. An Aurora channel consists of one or more Aurora lanes. Each Aurora lane is a full-duplex serial data connection. The devices that communicate across the channel are called channel partners. Figure illustrates this relationship.

The Aurora Protocol Specification defines the following:
• Physical layer interface
• Initialization and error handling
• Data striping
• Link layer
• Flow control

The ABFM models the behavior of the Aurora protocol and can be used to generate stimulus for and to monitor the response of an Aurora interface design, which is referred to as the device under test  (DUT). The ABFM provides parameterization of the protocol parameters (for example, the number of lanes) and that can be used to test any implementation of the Aurora protocol with little overhead.

The ABFM provides flexibility, a clean room implementation of Aurora, and improved performance over using another Aurora design to verify the DUT. The ABFM can be easily integrated into an existing verification environment specifically designed to test the DUT. Once the ABFM is integrated into the verification environment, it can communicate with the DUT using a programming language interface (PLI) for Verilog environments or a foreign language interface (FLI) for VHDL + Modelsim environment. Both PLI and FLI contain transaction based calls that are used to establish communication between the DUT and ABFM.

Downloads

• Aurora Protocol Specification & Bus Functional Model The Aurora protocol specification and Bus Functional Model are free and available for download after registration.	Click below for updates.
• Aurora LogiCORE™ IP Generate tailored HDL point solutions for the Virtex™-II Pro, Virtex-4 and Virtex-5 families with the Aurora LogiCORE IP supplied with the Xilinx ISE CORE Generator™. The user-configurable LogiCORE IP is available free of charge through ISE™ after registration and is updated in conjunction with standard Xilinx ISE IP Updates.	Click below for updates.