Agility Design Solutions Inc.

Harness the potential of ESL design for Xilinx FPGA.

Agility speeds the development of signal processing algorithms offering complete solutions for algorithm acceleration, prototyping and implementation in both software and hardware. The Agility products include unique software technologies for MATLAB® to C software implementation, C synthesis to FPGA logic, a rich portfolio of algorithm IP functions and a robust series of FPGA hardware platforms supported by C-based application programming interfaces.  Agility completes the solutions with services delivered by a team of expert designers to help customers meet deadlines and development requirements.

Formed through the merger of Catalytic Inc. and Celoxica’s ESL business, Agility delivers the world’s most successful and widely adopted ESL design and synthesis tools for Xilinx FPGA.  Combining technologies for algorithm implementation from MATLAB and C sources, Agility enables FPGA development for the software programmers and algorithm developers using their native algorithm description. 

Below are more facts about Agility:

Technology Brief Language Backgrounder

Suitability and Fit Xilinx Integration Getting Started

Technology Brief

Overview of the technology

• DK Design Suite – C-synthesis environment for algorithm to FPGA design
• Software design environment for algorithm implementation to Xilinx FPGA
• Hardware synthesis of algorithmic C code, using powerful Handel-C constructs directly to Xilinx device logic (DK Design Suite)
• Cycle-accurate simulation of C, Handel-C
• MATLAB and RTL co-simulation
• MCS – synthesis from MATLAB descriptions to ANSI-C
• Automatic synthesis of MATLAB code to C usable for any processor platform with an ANSI-C compiler
• PixelStreams – parameterized synthesizable video and image processing library
• Support for single and double precision floating point implementation
• APIs for automatic implementation of processor to FPGA logic interface, supporting MicroBlaze™ and PowerPC®
• Synthesis output in VHDL, Verilog and SystemC
• RC Series Boards - Integrated multi-feature FPGA development boards for image processing
• API interfaces for integrated algorithm synthesis to Xilinx, third-party and custom boards

History of the company and origins of the technology

• Company created from the merger of Catalytic Inc., a provider of MATLAB to C tools, with the ESL tools business from Celoxica, Ltd., the original provider of the Handel-C language
• The combined technology has sold over 500 licenses to over 100 companies worldwide and has been used in the development of 1000’s of FPGA designs
• Core C-synthesis technology created from research at Oxford University and subsequently was developed over a 10 year commercial period.
• The company has one of the largest and most successful University programs in the EDA industry
• The merged company, Agility Design Solutions Inc., is a private company based in Palo Alto, CA with offices in Austin, TX; Oxfordshire, UK; and Yokohama, Japan.  Agility is backed by top Silicon Valley investment firms.

Language Backgrounder

Which languages are supported?

• Agility supports algorithm implementation from MATLAB and ANSI-C, C++ and SystemC code.
• The C synthesis tools use the powerful Handel-C language to optimize design output from ANSI-C descriptions.
• The C synthesis tools produce VHDL, Verilog and SystemC design descriptions as outputs.
• The MATLAB synthesis tools produce efficient and readable C code that can be used on any platform with an ANSI-C compiler.

How is parallelization achieved?

• Agility technology enables explicit design control over parallelism to produce deterministic, optimized design results.
• Handel-C constructs such as the ‘par’ statement allow the user to define blocks of code which may run in parallel.
• Tool features aid the user in the determination of opportunities for parallelization and optimization.
• The Agility environment is flexible to allow users to specify parallel code at all levels of granularity.

Are multiple clock domains supported?

• Multiple clock domains are supported.
• Multiple blocks are supported with independent clocks and no size limitation.

Level of Abstraction - How different is it from coding in HDL?

• Design begins with C code source written at the algorithm level.
• Simple Handel-C constructs are added to portions of code to define parallel structures and optimize the design.
• Allows for rapid implementation of C algorithms to FPGA logi, and co-design to embedded processors using original C source.
• Delivers productivity improvements of 10x over RTL for complex signal processing algorithm implementation to FPGA.

Is floating point operation supported?

• Floating point libraries provide optimized implementation from code through the C-synthesis engine
• Library support for single and double precision floating point
• Includes standard operators such as MULT, DIV, ADD, SUB
• Library elements include transcendental and trigonometric functions
• Employs Xilinx logic structures for optimized implementation

Is an interface to Matlab supported?

• The MATLAB synthesis tool automatically produces C code from MATLAB descriptions
• Cycle accurate simulation interface for C/C++, Handel-C and Simulink from C synthesis tool
• Automatic generation of S functions in C synthesis tool

Are standalone function libraries available?

• The PixelStreams library contains source code for over 140 parameterized video and image processing IP blocks
• PAL (Platform Abstraction Layer) libraries for board level integration and platform abstraction
• Interface synthesis libraries for embedded processors supporting PowerPC and MicroBlaze
• Floating point function libraries integrated into C synthesis tools
• MCS function library includes over 300 blocks functionally equivalent to corresponding MATLAB functions. The blocks are synthesizable to ANSI-C source.

What format is the synthesis output?

• DK Design Suite produces Xilinx device data directly to Xilinx EDIF, integrated into Xilinx ISE tools to make bit-file programming transparent to the end user.
• MCS produces ANSI-C output from MATLAB descriptions
• DK Design Suite also can output RTL descriptions in VHDL (IEEE 1076 – 1999), Verilog (IEEE 1364-2001) and structural SystemC

Quality of results / Optimization scenarios

• Internal EDIF synthesis employs optimization features such as technology mapping and retiming for Xilinx FPGA
• DK Design Suite produces optimized RTL-quality results, while providing 10x productivity improvement for algorithm developers
• Familiarity with Handel-C constructs, and implications of coding in resulting hardware improves the quality of results while at all times allowing coding to be done from an algorithmic C source
• Sample results have shown designs over 300MHz in Virtex-5 logic, 50x improvement in algorithm speed over processor implementations, and 10% less logic than Verilog for a USB2 OTG design.
• System results for HW/SW system routinely exceed RTL design QoR, and provide much faster productivity.

Simulation and debugging flows

• DK supports mixed C/C++/Handel-C simulations for design migration and system simulation
• An integrated software IDE debugger allows cycle-accurate, bit exact simulation of code with ability to insert breakpoints, watch variables and monitor multiple code threads
• Co-simulation is provided with Simulink, SystemC and common RTL simulators

What is the learning curve?

• From customer experience, DK offers the lowest barrier to entry for algorithm developers new to FPGA design
• Starting with no knowledge of C synthesis or FPGA hardware, Agility provided 2 and 4 day training enables algorithm developers to produce hardware in days and be highly productive in weeks
• For experienced FPGA designers, DK provides improved productivity and ease-of-use for HW/SW co-design

Skill pre-requisite

• Some knowledge of hardware fundamentals is recommended to assist with understanding the basic concepts of parallel implementation, but can be derived from Agility training classes for those new to FPGA
• Basic understanding of C and/or C++ is required

Suitability and Fit

Who is the target audience?

• Algorithm developers wishing to implement using FPGA devices and embedded processors: includes system architects and software engineers responsible for design, prototyping and implementation of the algorithm to a system.
• System designers wishing to introduce FPGA designs to their DSP, GPU or embedded processor system to accelerate system performance

Which applications segments are targeted by this product?

• DSP, digital image and signal processing algorithms for any application area needing FPGA acceleration
• Agility application development experience includes customers in the following segments: Automotive, Aerospace and Defense, Consumer electronics, Industrial controls, Robotics, and High-Performance Computing

What are the characteristics of the target application?

• The application is designed from an algorithm modeled in C/C++ or MATLAB
• The system can not achieve desired performance using software-only implementations in processors or multi-core systems
• The algorithm is complex, and may contain thousands of lines of MATLAB or C code
• Portions of the design have been identified for acceleration in parallel processing hardware such as FPGA
• Modules can take advantage of the price/performance/power gains of custom FPGA logic over other implementation methods

Main value proposition?

• Productivity: fastest path from algorithm design to implementation
• System time to market improvements average 68% faster using DK
• Ease-of-use allows software designers to implement using FPGA and combined FPGA/processor systems
• Better algorithm design results in more optimized system and better system features
• Accelerated system performance, addition of FPGA logic can result in 10x-100x system algorithm performance improvements

How can you find out if your application is a good candidate for this tool methodology?

• Profile the software code to analyze bottlenecks for areas that can take advantage of FPGA logic
• The system requires a mix of processor and hardware implementation - Agility tools have been design to enable mixed HW-SW system modeling and implementation
• Agility can pre-process MATLAB code to identify optimizations and productivity benefits of introducing the MCS synthesis to C
• Identify and validate partition using the DK data flow analysis and partitioning methodology

Language and methodology limitations

• Agility tools is most beneficial for designs with complex algorithms partitioned between HW/SW implementations
• The MATLAB implementation tools are most helpful for designs with more than 1000 lines of MATLAB code
• The DK tool is best suited to algorithmically intensive designs starting with C or C++.  There is little benefit to using them for low level peripheral logic (i.e. memory controllers, etc.).
• There are no methodology limitations

Successful deployment examples

• A wide range of customer testimonials are available from Agility derived from over 5 years of customer design experience using these tools.  Please see www.agilityds.com for more specific information.
• The DK Design Suite has over 100 customers and has been used in 1000’s of successful algorithm design implementations to FPGA. It is the most heavily used C-synthesis tool for FPGA available on the market.

Customer testimonials

• A wide range of customer testimonials are available from Agility. Please see www.agilityds.com for more specific information.

Pricing

• Pricing is dependent on tool configurations
• Agility has entry level solutions for all budgets
• Contact sales@agilityds.com for more information

Xilinx Integration

Which Xilinx devices/architectures are supported?

• Virtex™-5
• Virtex-4 FX, LX, SX
• Virtex-II Pro
• Virtex-II
• Spartan™-3
• Spartan-II

Which Xilinx Boards are supported?

• Algorithm programming to Xilinx devices from DK is available for all Xilinx boards directly to EDIF or through RTL output
• Agility sells a wide range of Xilinx-based development boards for prototyping
• Board support libraries and APIs are provided for the most common Xilinx-based boards on the market

Which Xilinx CPUs are supported?

• PowerPC®
• MicroBlaze™
• PicoBlaze™

Is the Virtex-4 FX APU supported?

• Some automated support is available for the Virtex-4 FX APU. Contact Agility for more information.

Inference of Xilinx Library components

• Agility technology has been optimized to infer available Xilinx Library components

Benchmark studies targeting Xilinx

• A wide range of benchmarks are available from Agility. These include HPC algorithms running 30x-100x faster using Xilinx logic, design projects comparing RTL with C code for algorithmic implementation, and many examples of algorithm design for DSP, image and signal processing.  Contact Agility for more information on an example relevant to your business.

Flow integration with EDK/XPS, ISE, System Generator (Implementation)

• The DK Design Suite is fully integrated with Xilinx ISE place and route tools to make the programming of the FPGA transparent to the end user. I
• Integration is available for flows using System Generator and EDK.
• The focus of Agility is providing a seamless flow for design implementation from algorithm through Xilinx tools.

Flow integration with EDK/XPS, ISE, System Generator (Simulation)

• Agility tools support cycle accurate simulation of C-based designs and integrate with popular RTL simulators and Mathworks Simulink.

Getting Started

How to get started

• Buy online for a Xilinx ESL Starter Kit including a Spartan-3 FPGA development board and the DK Design Suite
• Xilinx development kits are also available for a range of applications.
• Contact Agility at sales@agility.com for more information on the tools for your algorithm implementation.

Design examples for various Xilinx boards

• Agility tools are used in a wide range of applications and physical form factors in embedded design and high performance computing
• Agility and its partners provide support for over 100 different Xilinx based boards from desktop to GiGE, to PCI, PCIexpress and HyperTransport and many combinations of devices and peripherals.  See www.agilityds.com for more information.
• Multiple design examples and tutorials are available with Agility design software and developer kits.

Info kits available?
(i.e., bundling of boards, software, examples for an integration out of the box experience)

• The Xilinx ESL Starter kit is available from www.agilityds.com
• A range of off-the-shelf evaluation and development kits are provider that include ESL software, design IP and tutorials and Xilinx-based boards
• Agility experience and board APIs provide access to the largest range of development boards available to C to FPGA algorithm developers.
• Contact sales@agilityds.com for more information

Design services / consultancy available?

• Design consultancy is available from experience engineering experts on all aspects of development from algorithm to software to hardware implementation to board development. Contact sales@agilityds.com for more information.