Bluespec
Bluespec reduces design time and errors.
Bluespec presents the hardware designer an exciting new way to simplify the complexity of constructing control logic while retaining full control over the architecture and performance of the design. Bluespec's ESL synthesis toolset enables hardware designers a much faster way to explore alternative architectures and micro-architectures and make feature changes, and with significantly fewer errors.
Below are more facts about Bluespec:
Technology Brief
Overview of the technology
- Bluespec presents the hardware designer an exciting new way to simplify the complexity of constructing control logic while retaining full control over the architecture and performance of the design
- Bluespec’s ESL synthesis toolset for control logic and complex datapath designs significantly accelerates hardware design & reduces verification costs delivering:
- Over a 50% reduction in time to a verified design
- Less than 50% of the bugs compared to RTL design
- Design exploration and feature changes can be made correctly and much more quickly
History of the company and origins of the technology
- Bluespec was founded in 2003 to commercialize the ESL synthesis toolset
- The patented Bluespec technology is based on over eight years of research at MIT, starting in 1997. The development of the synthesis tool started in 2000 originally as part of a semiconductor company, until Bluespec was incorporated
Language Backgrounder
Which languages are supported?
- Based on SystemVerilog syntax, Bluespec leverages familiar hardware semantics to ease the learning curve for hardware engineers and ensure that hardware quality matches that of hand-coded
- Bluespec SystemVerilog introduces rules and interface methods for behavioral description, adding a powerful way to express complex concurrency & control:
- Across multiple shared resources
- Across module boundaries
How is parallelization achieved?
- With Bluespec, concurrent behavior is expressed implicitly. Bluespec uses the traditional hardware semantic model of cooperating finite state machines
- Bluespec uses rules, which simply describe under what conditions state element(s) are updated, to express concurrent operations. Rules are unsequenced atomic transactions. The compiler introduces the scheduling and the muxing for shared resources
Are multiple clock domains supported?
- Yes
- Bluespec includes integrated clock management and formal clock connectivity verification to enhance its multiple clock domain (MCD) support
- By incorporating clocking into its semantic model, Bluespec's toolset simplifies complex clock topology implementations and ensures that mis-connections are caught at the time of synthesis
Level of Abstraction - How different is it from coding in HDL?
- Bluespec provides a significantly higher level of abstraction than Verilog, SystemVerilog, VHDL and SystemC in the following dimensions:
- Behavioral descriptions. Bluespec uses rules and interface methods for behavioral description, adding a powerful way to express complex concurrency & control:
- Across multiple shared resources
- Across module boundaries
- Structural descriptions. Bluespec has significantly higher ways to describe and perform:
- High-level abstract types
- Powerful static checking
- Powerful parameterization
- Powerful static elaboration
- Advanced clock management
Is floating point operation supported?
- Yes, designers can express the functionality of the design and defer specific implementation designs till later in the process – as late as RTL synthesis. Alternatively, they can use floating point library elements that are user definable. Bluespec supplies an IEEE floating point multiplier as a starter kit for use or modification by users that want full control over these execution units
Is an interface to Matlab supported?
- No, there is no specific support for Matlab
Are standalone function libraries available?
- Yes
- Examples of library elements include data structures and containers such as FIFOs and registers, advanced data types, circuits (such as LFSR and CompletionBuffer), interface types, multiple clock domain synchronizers
- Examples of useful circuits include GET/PUT transactors, credit-based interfaces, polymorphic functions for interconnects, transformations, matrix math
What format is the synthesis output?
Quality of results / Optimization scenarios
- With Bluespec, the quality of results is comparable to hand-coded RTL
- Designers maintain full control over specifying the architecture and micro-architecture of the design – this gives them the same control as with RTL design, but with the ability to make changes much faster and more correctly
Simulation and debugging flows
- A design is simulated and debugged using the source level simulation tool, Bluesim, or by simulating the generated Verilog RTL
- Bluespec provides unparalleled transparency to the RTL, as well as readability of the RTL, enabling designers to work directly with the Verilog RTL output
- The user typically uses a debugger such as Novas’ Verdi (or Debussy) for direct probing from the waves to the source Bluespec SystemVerilog
What is the learning curve?- Basic training for initial design work takes less than a week. At that point, designers are productively using Bluespec. Advanced training can be obtained from Bluespec at any time
Suitability and Fit
Who is the target audience?
- Hardware architects and design engineers that are designing hardware with complex control logic and data paths, such as processing elements, DMA controllers, memory controllers, complex algorithms such as H.264, DVB-H or telecom and datacom protocols including throughput and latency sensitive packet processors
- Bluespec is wonderful for speeding up the development of glue logic that fits inside an FPGA. Further, many processors, microcontrollers, network engines, search engines, disk controllers, etc. are perfect target applications
Which applications segments are targeted by this product?
- Processors, microcontrollers, disk controllers, automotive controllers
- Multi-media such as H.264, DVB-H, DTV
- Low Power handheld applications such as handsets, DVD players
- High performance applications such as telecom and datacom where throughput is important
What are the characteristics of the target application?
- Particularly well suited to designs rich in control logic and complex datapaths (those with bypassing, stalls, muxing, and feedback)
Main value proposition?
- Half the time from requirements to FPGA
- Over 2X fewer bugs
- Promotes rapid and correct design explorations as well as architecture and micro-architecture changes to meet device timing
How can you find out if your application is a good candidate for this tool methodology?
- Bluespec can be used successfully wherever Verilog or VHDL would be used
- Typically, it would involve the entire FPGA design or a significantly sized IP component of the design
- Bluespec is particularly effective with designs involving complex control logic
Language and methodology limitations
- No known limitations versus RTL design
Successful deployment examples
- There are many examples of code for challenging applications on the Bluespec web site. They range from the heart of a memory controller to fast interconnect architectures to microprocessors
Customer testimonials
- There are many papers that have been presented at peer-reviewed conferences that highlight the Bluespec technology These range from papers at ICCAD to Memocode to the Conference of Designing Correct Circuits. Bluespec believes that these papers, with their rigorous review process, and selection for technical merit, offer a better perspective than mere marketing sound bites
- Bluespec’s website offers customer testimonials
Pricing
- Pricing is according to time-based floating licenses (for synthesis and simulation) or project-based
Xilinx Integration
Which Xilinx devices/architectures are supported?
- As Bluespec generates standard Verilog RTL without requiring a technology library, there are no device limitations
Which Xilinx boards are supported?
- There is no specific support for Xilinx evaluation boards
Which Xilinx CPUs are supported?
- Bluespec can be used to instantiate any RTL-based IP. Connectivity and instantiation is under full architecture and micro-architecture control of the designer
Inference of Xilinx Library components
- Bluespec can be used to instantiate any RTL-based IP
Benchmark studies targeting Xilinx
Flow integration with EDK/XPS, ISE, System Generator (Implementation)
- Bluespec produces very generic Verilog that flows seamlessly into all RTL synthesis tools. Directives, pragmas and comments make their way into the generated RTL code for downstream processing
Flow integration with EDK/XPS, ISE, System Generator (Simulation)
- Bluespec supports all Verilog based simulators. A specific compile option will automatically detect the simulator of choice on your machine and launch the simulation. All debugging is done through the viewform viewer provided by Novas’ Verdi (Debussy). Alternatively, we issue a tcl kit to integrate the viewer of your choice
- If you use Bluesim, our source level simulator, you have the option of replacing any Bluespec method call with a “C” function, allowing you to imbed arbitrary C code into your simulation – e.g. for checking your s/w drivers
Getting Started
How to get started
- Please send us an email at xilinxinfo@bluespec.com with your contact details. A technical representative will be in touch to discuss your project and recommend the best approach to training and support to ensure that your project will be successful
- Please download the Reference Guide or look at some of the copious material on our web site to get an understanding of how the technology works
- Give us a call at +1 781 250 2200 and ask to speak with sales
Design examples for various Xilinx boards
Request for evaluation
Sales kits available?
(i.e. bundling of boards, software, examples for an integration out of the box experience)
How to get design services
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