Impulse
Create FPGA-accelerated systems faster with Impulse C.
Describe hardware accelerators algorithmically, using C-language, and compile directly into optimized logic ready for use with Xilinx FPGAs. Use the Impulse tools to quickly prototype mixed software/hardware systems and perform design iterations in just minutes or hours, instead of days or weeks. If you are using embedded MicroBlaze™ or PowerPC® processor cores, CoDeveloper can automatically generate the required hardware/software communication channels using FSL, APU and other Xilinx interfaces.
Below are more facts about Impulse:
Technology Brief
Overview of the technology
- Allows C-language applications to be compiled into FPGA logic in the form of synthesizable, optimized HDL
- Complements popular FPGA design tools and methods
- Also complements popular C programming and debugging environments
- Increases design productivity and creates new opportunities for design experimentation, prototyping and rapid software-to-hardware conversion
- Ideal for image processing, DSP, data compression, embedded systems and high-performance FPGA computing
History of the company and origins of the technology
- Founded October, 2002 in Kirkland, Washington
- Founded by programmable logic industry veterans
- Represents third generation of PLD/FPGA tools
Language Backgrounder
Which languages are supported?
- Supports ANSI C, with Impulse C library extensions
- Any Impulse C application can be compiled and executed for simulation purposes using standard C tools
How is parallelization achieved?
- The Impulse C compiler and optimizer automatically generate parallel logic by scheduling C operators, including entire blocks of C code spanning multiple lines, and is capable of generating loop pipelines for increased parallelism and performance
- There is no need to insert "par" or other RTL-equivalent statements to generate parallel logic
- Impulse C compiler pragmas allow the programmer to control the generation of loop pipelines, the unrolling of loops and the size of the generated logic for each critical code segment
- For system-level parallelism, Impulse C includes library functions allowing multiple parallel C processes to be described and interconnected using a communicating sequential process (CSP) programming model
Are multiple clock domains supported?
- For applications consisting of multiple software and/or hardware processes, Impulse C provides an elegant, timing-independent method of describing inter-process communication and synchronization
- When mapping Impulse C applications to platforms that include embedded MicroBlaze or PowerPC processors, the Impulse CoDeveloper compiler is capable of generating the required FSL/APU/PLB interfaces—automatically
- Multiple clock domains are supported in this programming model, through the use of optional dual-clock stream and signal interfaces to each generated process
Level of Abstraction - How different is it from coding in HDL?
- Impulse C represents an untimed, behavioral method of high-level algorithm design
- Unlike other “C-like” languages for FPGA design, Impulse C is based on ANSI C and is fully compatible with standard C compilers and debuggers. Impulse C is not “RTL within C syntax”
- Any application you write in Impulse C can, by definition, be compiled and debugged using standard C development tools including Microsoft Visual Studio, Eclipse and GCC/GDB-based tools
Is floating point operation supported?
- Single and dual precision floating point is supported for Xilinx FPGA targets, including pipelined floating point operators
- The Impulse CoDeveloper automatically generates references to Xilinx COREGen floating point libraries from C language floating point operations
Is an interface to Matlab supported?
- There is currently no support for Matlab or Simulink design flows
Are standalone function libraries available?
- The Impulse C compiler supports the use of user-specified, optimized HDL libraries
- Impulse can provide application-specific optimized libraries on a services basis
- There are extensive application examples provided with the product
What format is the synthesis output?
- Generates synthesizable, simulatable and human-readable VHDL and Verilog
Quality of results / Optimization scenarios
- Quality of results are greatly impacted by the skills of the programmer, just as they are when coding in HDLs
- Experienced Impulse C programmers are able to generate logic outputs that in many cases rival hand-coded HDL in terms of size and algorithm throughput
- Extremely fast compile/optimize/analyze loop enables a high degree of design experimentation, leading to improved QOR
- Impulse C optimization pragmas allow tight control over generated hardware, for example the use of DSP blocks
- Hand-optimization of the generated HDL is possible, and in some cases may be recommended for highest possible performance
Simulation and debugging flows
- Any Impulse C application can, by definition, be compiled and simulated for functional verification purposes using standard C development tools such as Visual Studio, CodeWarrior, GCC/GDB or Eclipse
- An integrated Application Monitor allows parallel, multiple-process applications to be observed during software simulation, allowing data movement and synchronization issues to be analyzed and debugged
- For debugging of cycle-accurate and bit-accurate behaviors, Impulse C includes an optional cycle-accurate HDL-to-C reverse translator and source-level debugger
- Hardware-savvy developers can simulate the generated HDL files using popular HDL simulators
What is the learning curve?
- Impulse C is designed to allow software engineers to become FPGA designers with little or no assistance from more-experienced hardware designers
- An extensive library of Impulse C examples and tutorials make it easy to get started: just select a sample project and modify it to meet your needs
- Semi-automated Design Assistant and template generation features make it easy to created entirely new Impulse C applications, including applications involving multiple connected processes
- A 450-page book, Practical FPGA Programming in C, presents FPGA programming using Impulse C and describes programming and optimization techniques, as well as techniques for hardware/software co-design
Skill pre-requisite
- Knowledge of C programming is a prerequisite
- Prior experience with HDLs is an advantage, but not required
- No knowledge of hardware/FPGA design is needed
- Software programmers with absolutely no VHDL or Verilog experience, and no prior experience with FPGAs have successfully used Impulse C to create FPGA-accelerated applications
Suitability and Fit
Who is the target audience?
- Software programmers wishing to take advantage of FPGAs for high performance co-processing
- Experienced FPGA designers seeking a faster path to hardware for prototyping purposes
- Application developers creating video and image processing, DSP, data compression and security, embedded systems and FPGA-based enterprise and scientific computing
Which applications segments are targeted by this product?
What are the characteristics of the target application?
- Applications that are most suited to Impulse C are computationally intensive and involve streaming and/or shared memory for data communications
- Applications that are dominated by control statements and have relatively little actual computation may not benefit from C-to-hardware compilation
- Small applications that are easily coded in VHDL or Verilog (such as simple decoders) may not be well suited to Impulse C
How can you find out if your application is a good candidate for this tool methodology?
- Assessing the suitability of an application:
- Is there a C-code implementation already running on a traditional processor, or is the algorithm easily described in C?
- Are there one or more critical algorithms (e.g. inner code loops) that can be partitioned into distinct processing elements?
- Is the application computationally intensive, or data intensive? Will data communication overwhelm any benefit of hardware algorithm acceleration?
Language and methodology limitations
- Impulse C is based on standard ANSI C, but not all features of C can be compiled to hardware
- Impulse C is not intended as a complete replacement for HDL/RTL coding methods and tools
- Impulse C should be viewed as another tool in the toolbox, one allowing C programmers to more quickly generate working systems from higher-level algorithms
Successful deployment examples
- Impulse has been part of successful projects at General Dynamics, Mitsubishi Research, Hitachi, Canon, Toyota, Draper Labs, LANL, U.S. Navy, Air Force, the University of Washington, the University of Montana, the University of Florida, and many others
Customer testimonials
Pricing
- Annual licenses (all Xilinx targets, no feature restrictions) start at $7,500.00
- Perpetual node-locked licenses start at $16,500.00
- Floating licenses start at $21,500.00
- Contact sales@ImpulseC.com for details
Xilinx Integration
Which Xilinx devices/architectures are supported?
- All Xilinx FPGA families are supported via generated VHDL and Verilog outputs
Which Xilinx CPUs are supported?
- PowerPC is supported via automatically generated APU and/PLB software/hardware interfaces
- MicroBlaze is supported via automatically generated FSL and PLB interfaces
Inference of Xilinx Library components
- Xilinx blocks (such as floating point libraries and RAM blocks) are inferred from the user’s C-code, and are generated by the compiler as netlist references and/or inferred during synthesis via generated RTL code styles
Benchmark studies targeting Xilinx
Flow integration with EDK/XPS, ISE™, System Generator (Implementation)
- Extensive tutorials are provided. The basic steps are:
- Describe in C
- Partition algorithm into communicating software and hardware processes as appropriate
- Specify a target platform (e.g. “Xilinx Virtex®-4 APU”)
- Invoke compiler to generate hardware, including processor interface wrappers as appropriate
- Export from Impulse CoDeveloper to Platform Studio project
- Use Platform Studio to attached generated “pcore” IP blocks to processor bus
- Synthesize the complete system
- Download to the device
Flow integration with EDK/XPS, ISE, System Generator (Simulation)
- Generated HDL files are fully compatible with RTL simulation tools
- An Impulse C HDL simulation tutorial is provided with CoDeveloper
Getting Started
How to get started
- Impulse C tutorials:
- Impulse C into ISE
- Impulse C into Platform Studio for MicroBlaze/FSL
- Impulse C in to Platform Studio for PowerPC/APU
Design examples for various Xilinx boards
- Pre-built, ready to download examples are available, including ready-to-run examples for the following boards
- Spartan®-3 1800A XtremeDSP™ board
- ML401 board
- ML403 board
- ML410 board
- ML501 board
- ML555 board
- Cray XD1
- DRC Computing
- Pico Computing E-14 and E-16
- and others
Request for evaluation
Sales kits available?
(i.e. bundling of boards, software, examples for an integration out of the box experience)
- Yes, multiple kits are available
- Purchase from this site link and get special offers
- University Package Board Promotions
- Commercial Package Board Promotions
Design services / consultancy available?
How to get design services
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