Synplicity, Inc.

High-level Algorithmic Modeling And True DSP Synthesis

The Synplify DSP tool provides a unique ESL synthesis methodology that realizes significant productivity and portability advantages over traditional HDL design flows. The Synplify DSP software combines a high-level modeling library offering multi-rate and vector functions with a powerful DSP synthesis engine that allows designers to quickly capture complex algorithmic behavior. The Synplify DSP synthesis engine allows designers to automatically implement and explore area/speed-optimized HDL architectures from a single model. This eliminates the burden of hand coding functions and architectural optimizations, achieves significantly faster design capture and time to market and enables rapid design exploration that results in improved quality and lower cost.

Below are more facts about Synplicity:

Technology Brief Details

Suitability and Fit Xilinx Integration Getting Started

Technology Brief

Overview of the technology

• Rapidly create technology-independent DSP algorithm models that are implement-able across Xilinx FPGA device families
• Comprehensive DSP library with comprehensive multi-rate and vector math support
• Easy fixed-point quantization and analysis tools with up to 128-bit precision
• User-extensible and customizable IP methodology
• Wireless IP library includes Viterbi Decoder, CIC, multi-rate and CIC filtering, frequency synthesis, and more
• Black-box flow supports Xilinx IP cores
• DSP Synthesis engine creates architecturally optimized RTL implementation and test bench
• Saves months of hand coding with automatic optimizations for pipelining, folding, and multi-channelization
• Enables rapid architectural exploration and implementation into Virtex™-II Pro, Virtex-4, Virtex-5, and all Spartan™-3 devices.

Lauguage Background

Which languages are supported?

• Simulink Synplify DSP blockset
• MATLAB® M-language
• Verilog/VHDL

How is parallelization achieved?

• Parallelization is easily and concisely created using vectorized operations and IP functions from the modeling environment and Synplify DSP blockset.
• The DSP synthesis engine can automatically serialize the implementation for area improvement, or pipeline the algorithm to meet timing constraints.  The architectural optimizations are target-aware to incorporate the timing and technology characterization of the target device.  The employs resource sharing and scheduling on expensive operations and automatically accommodates multi-rate clock domains to achieve higher sharing and lower area.

Are multiple clock domains supported?

• Yes, multi-rate clock domains are supported with flexible choice of clocking strategies.
  

Level of Abstraction - How different is it from coding in HDL?

• Synplify DSP leverages the Simulink Model-based design environment which abstracts away specific logic design details like resets, enables, etc.
• Fixed-point data types and sample rates are automatically captured and propagated as the designer instantiates and creates the model saving significant effort in starting designs
• Comprehensive IP library like FFT, Viterbi Decoder, DDS, CORDIC math functions, etc. enables rapid creation in application-specific domains.
• Vector support allows high dimensional signals and operations to be described in a single datapath (up to 2048 in length)
• M-control raises the abstraction level for control logic and state-machines allowing the use of M-language description with automatic quantization, persistent variables for storage, and software-like in-line debugging features.
• Powerful tools are available to analyze the algorithm behavior, waveforms, spectrums, etc. in both a graphical and Matlab scripting environment
• The Synplify DSP blockset and modeling environment is maintained at a high-level of hardware and architectural abstraction making design capture much easier.
• The DSP Synthesis engine can automatically create target-aware optimized architectures which eliminates hand-coding and makes exploration much more efficient.

Is floating point operation supported?

• The modeling environments supports floating-point override mode to analyze and isolate quantization effects.
• Implementation for floating point operations is not currently supported, however, most models support up to 128-bit fixed-point precision.
  

Is an interface to MATLAB supported?

• Yes, the M-control feature allows embedded Matlab which can be synthesized and optimized into RTL.  Key features include automatic quantization, persistent variables for storage, and software-like in-line debugging features as well advanced operations like multiply, add.

Are standalone function libraries available?

• Black-box flow supports instantiation of any external third party HDL-based IP, including LogiCore and Xilinx System Generator models.

What format is the synthesis output?

• Synplify DSP generates synthesizable Verilog HDL, and VHDL RTL code.
• Synplify DSP also generates the project, constraint, and other necessary files for logic synthesis in Synplify Pro

Quality of results / Optimization scenarios

• The Synplify DSP synthesis engine allows user-controlled architectural optimizations to achieve significant speed and area improvements in implementation.  This leads to significantly better results than hand-coded design flows.
• The Synplify DSP synthesis engine makes target-aware micro-architectural optimizations for key IP blocks such as FIR filters.
• The optimization engine includes an advanced timing engine which accurately estimates timing for Xilinx devices.
• Area optimizations automatically leverage multi-rate behavior to increase resource-sharing in slower clock domains.  This can result in up to 75% area reduction or higher for high decimation or interpolation factors.
• The Synplify DSP design flow automatically infers and maps appropriate operations into on-chip resources of Xilinx FPGAs including DSP48, DSP48E, block RAM, distributed RAM, SRLs, Spartan and Virtex-II Pro FPGA multipliers, etc.

Simulation and debugging flows

• Fully automated verification flow requiring only the input/outputs of the model simulation
• Synplify DSP automatically creates an RTL test bench with batch files for Modelsim, ActiveHDL, and other simulators to use the input/output simulation data to re-simulate using the RTL output.  The same test bench can be used to verify gate-level netlists as well.

• Maximal reuse of test bench and test vector eliminates error-prone test bench/vector reconstruction.

What is the learning curve?

• Extremely easy with comprehensive documentation, reference examples, and training.  Very little hardware design or HDL coding is required.

Skill pre-requisite

• Basic system and modeling design experience is required along with DSP discrete-time and fixed-point quantization concepts.  Synplify DSP leverages the Simulink Model-based simulation environment, so previous experience is helpful, but because it is a graphical environment the learning curve is very quick.
• No knowledge of FPGA and hardware design is necessary to create DSP models, but is helpful during the downstream implementation flow (logic synthesis and place and route)

Suitability and Fit

Who is the target audience?

• System architects and Algorithm designers – fixed-point algorithm design which is easy to hand-off to hardware teams, or who want to perform rapid design space or architectural exploration studies, or do their own FPGA prototyping
• System engineers – implementing and distributing compute-intensive algorithms into FPGA platforms or create rapid prototypes of algorithms
• Hardware, FPGA, and ASIC engineers - implementing algorithms directly into an FPGA or ASIC
• Verification engineers – fast prototyping and accelerated verification in FPGA hardware

Which applications segments are targeted by this product?

• Synplify DSP is well suited for wireless algorithm design including digital RF/IF processing and forward error correction, digital multimedia for audio, video, encryption, high performance computing.

What are the characteristics of the target application?

• High-performance, high sample-rate, compute intensive algorithms that need dedicated RTL/FPGA implementation
• Wireless, Mil/Aero, Industrial, and Consumer products required algorithm IP cores
• Hardware Accelerated embedded Systems

Main value proposition?

• Faster time to market – eliminates months of logic-level and architectural optimization and coding, and delivers high quality implementation that utilizes all Xilinx advanced device resources.
• Ease of use – the Synplify DSP library and modeling environment offers the easiest design capture experience for multi-rate and vector-based DSP algorithms.
• Portability and Design Reuse – easily create and manage algorithmic IP at a high-level and leverage this ROI across all Xilinx device families.
• Lower Cost – rapid design exploration allows fast application-specific tuning and more optimal results. 
• Lower Risk – more predictable design capture and implementation process with fast design capture and architectural exploration features.

How can you find out if your application is a good candidate for this tool methodology?

• Application requires DSP, mathematical, or algorithmic implementation into FPGA
• The design has been described in a high-level language such as Matlab M-code or C
• The design uses multi-rate algorithmic behavior
• Application required IP cores like FFT, FIR filters

Language and methodology limitations

• There are no methodology limitations

Successful deployment examples

• Many success stories are available at Synplicity website:  http://www.synplicity.com/literature/

Customer testimonials

• Testimonials are available at the Synplicity website: http://www.synplicity.com/literature/

Pricing

• Pricing ranges for term, perpetual, node-locked, floating and team licenses. Please contact Synplicity at:  http://www.synplicity.com/products/dsp_solutions.html

Xilinx Integration

Which Xilinx devices/architectures are supported?

• Virtex-5
• Virtex-4
• Virtex-II Pro
• Virtex-II
• Spartan-3
• Spartan-3 DSP

Which Xilinx CPUs are supported?

• N/A

Is the Virtex-4 FX APU supported?

• N/A

Inference of Xilinx Library components

• DSP48, DSP48E, Block RAM, Distributed RAM, SRLs, Spartan and Virtex-II Pro FPGA Multipliers

Benchmark studies targeting Xilinx

• The optimization engine includes an advanced timing engine which accurately estimates timing for Xilinx devices.
• Area optimizations automatically leverage multi-rate behavior to increase resource-sharing in slower clock domains.  This can result in up to 75% area reduction or higher for high decimation or interpolation factors.
• The Synplify DSP design flow automatically infers and maps appropriate operations into on-chip resources of Xilinx FPGAs including DSP48, DSP48E, Block RAM, Distributed RAM, SRLs, Spartan and Virtex-II Pro FPGA Multipliers, etc.
• For more details please refer to the Synplify DSP whitepapers at http://www.synplicity.com/literature/

Flow integration with EDK/XPS, ISE™, System Generator (Simulation)

• Synplify DSP can export implementations into System Generator for system-level integration and EDK tools from Xilinx.  Synplify DSP requires Synplify Pro for logic synthesis.

Flow integration with EDK/XPS, ISE, System Generator (Simulation)

• Synplify DSP support Modelsim SE, PE, and XE for cosimulation.
• Synplify DSP black-box features support Xilinx LogCORE™ IP.

Getting Started

How to get started

• Contact Synplicity for training and an evaluation license: http://www.synplicity.com/products/dsp_solutions.html

Design examples for various Xilinx boards

• Synplify DSP includes reference designs and examples that map to Xilinx boards.  Please contact Synplicity for more information: http://www.synplicity.com/products/dsp_solutions.html

Info kits available? (i.e. bundling of boards, software, examples for an integration out of the box experience)

• Synplify DSP includes reference designs and examples that map to Xilinx boards and also includes worldwide DSP specialists and FAEs who can support Xilinx FPGA hardware.  Please contact Synplicity for more information: http://www.synplicity.com/products/dsp_solutions.html

Design services / consultancy available?

• Synplicity has a range of partners and third party sources for supporting Xilinx FPGA hardware, prototyping, and DSP algorithm design.  Please contact Synplicity for more information:  http://www.synplicity.com/