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Image Signal Processing (ISP) Pipeline

  • 产品编号: logiISP
  • 供应商: Xylon d.o.o.
  • 联盟计划等级: Premier

产品描述

The logiISP-UHD Image Signal Processing Pipeline IP core is an Ultra High Definition (UHD, including 4K2K) ISP pipeline designed for digital processing and image quality enhancements of an input video stream in Smarter Vision embedded designs based on Xilinx All Programmable devices. The logiISP-UHD IP core accepts diversely formatted video inputs generated by different sensors and removes defective pixels, de-mosaics Bayer encoded video, makes image color and gamma corrections, filters the noise from the video, collects video analytics data for various control algorithms and manipulates video data formats and color domains. In addition to the standard IP core deliverables, Xylon offers licensable Auto White Balancing (AWB) and Auto Exposure (AE) processor-based control algorithms that work with the video analytics data collected by the ISP pipeline.

The logiISP IP core can be easily combined with the logiHDR High Dynamic Range (HDR) Pipeline IP core into advanced video processing pipeline capable to extract the maximum detail from high contrast scenes, i.e. scenes with objects highlighted by a direct sunlight and objects placed in extreme shades.


主要特性与优势

  • Complete and configurable Ultra High Definition ISP pipeline
  • Configurable ISP blocks: Defective Pixel Correction, Color Filter Array Interpolation, Image Statistics, Image Enhancement, Color-Space Converters and others
  • Digitally processes and enhances the quality of an input video stream and collects video statistics data
  • Evaluation IP core and the bit-accurate C model available on request
  • Fee-based license extension for the AWB&AE
  • IP deliverables include the software driver, documentation and technical support
  • Input video formats: Raw Bayer, RGB and YCrCb; 8/10/12-bit per pixel
  • Parallel pixel processing of 1, 2 or 4 pixels per clock
  • Supports resolutions up to 7680x7680, including 4K2Kp60 (3840x2160)
  • Video input and output are ARM AMBA AXI4-Stream protocol compliant

特色技术文档

器件实现矩阵

面向此核实现范例的器件使用矩阵。联系供应商了解更多信息。

系列 器件 速度等级 工具版本 硬件验证? LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K325T -3 Vivado 2015.4 Y 0 9164 80 28 0 0 304
Zynq-7000 Family XC7Z020 -1 Vivado 2015.4 Y 0 9157 78 28 0 0 182

IP 质量指标

综合信息

数据创建日期 Sep 25, 2017
当前 IP 修订号 2.0
当前修订日期已发布 Feb 22, 2016
第一版发布日期 Dec 09, 2014

Xilinx 客户的生产使用情况

Xilinx 客户成功生产项目的数量 10
可否提供参考? N

交付内容

可供购买的 IP 格式 Netlist
源代码格式 VHDL
是否包含高级模型? Y
模型格式 C
提供集成测试台 N
是否提供代码覆盖率报告? N
是否提供功能覆盖率报告? N
是否提供 UCF? N
商业评估板是否可用? Y
是否提供软件驱动程序? Y
驱动程序的操作系统支持 no OS

实现方案

代码是否针对 Xilinx 进行优化? Y
标准 FPGA 优化技术 Inference, Instantiation, UltraFast Design Methodology
定制 FPGA 优化技术 None
所支持的综合软件工具及版本 Xilinx XST
是否执行静态时序分析? N
AXI 接口 AXI4-Stream, AXI4-Lite
是否包含 IP-XACT 元数据? Y

验证

是否有可用的文档验证计划? Executable and documented plan
测试方法 Both
断言 Y
收集的覆盖指标 Assertion
是否执行时序验证? Y
可用的时序验证报告 N
所支持的仿真器 Mentor ModelSIM

硬件验证

在 FPGA 上进行验证 Y
所使用的硬件验证平台 MicroZed Embedded Vision Kit
已通过的行业标准合规测试 N
是否提供测试结果? N
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