DDR/DDR2 PHY only solution
The Spartan®-6 FPGA DDR/DDR2 SDRAM PHY core was developed by Northwest Logic for distribution by Xilinx. This reference design core was designed to meet the needs of customers who have custom or legacy DDR/DDR2 controllers and require just the physical interface (PHY) solution for Spartan-6 devices. The PHY core reference design files and documentation can be downloaded directly from Xilinx (see links at right). Support for the PHY only solution is also provided by Xilinx.
DDR/DDR2 Complete Controller (w/PHY) Solution
The Spartan-6 FPGA DDR/DDR2 SDRAM Controller core was developed by Northwest Logic to offer customers a complete and easy to use “off the shelf” DDR/DDR2 memory interface solution. This core is distributed and supported by Northwest Logic and uses the same PHY technology as the PHY only solution above. The controller fully supports features such as Additive Latency, differential DQS, and on-die termination (ODT). The controller includes a command queue which allows new commands to be issued on every clock cycle. This results in no delay between requests, enabling up to 100% memory throughput (not including refresh cycles), even for the shortest burst length setting (BL4). Contact Northwest Logic for more information.
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