Distributed Memory Generator

产品详细资料

• System Requirements
• 向Xilinx询问该核的问题

文档

• Xilinx End User License Agreement
• 分布式存储器生成器
• Release Notes (PDF)

支持器件系列

• Virtex-6 -1L
• Virtex-6 HXT
• Virtex-6 LXT
• Virtex-6 SXT
• Virtex-5 FXT
• Virtex-5 LX
• Virtex-5 LXT
• Virtex-5 SXT
• Virtex-4 FX
• Virtex-4 LX
• Virtex-4 SX
• Virtex-4 XA
• Virtex-II Pro
• Virtex-II
• Virtex-E
• Virtex
• Spartan-6 LX
• Spartan-6 LXT
• Spartan-3A DSP
• Spartan-3E
• Spartan-3 XA
• Spartan-3
• Spartan-II
• Spartan-IIE

The Distributed Memory Generator IP core utilizes Xilinx Synthesis Technology (XST) to create a variety of memory structures using Select RAM. It can be used to create Read Only Memory (ROM), single-port Random Access Memory (RAM), and pseudo-dual port RAM as well as SRL16-based RAM. The core supports data widths of up to 1024 bits. Memory depths ranging from 16 to 65,536 words are supported for all families except Virtex®, Virtex-E and Spartan®-II. For these families, depths may range from 16 to 4096 words. Additional options include support for simple registering of inputs and outputs and asynchronous and synchronous resets for output registers.

The Distributed Memory Generator should be used in all new designs wherever a Distributed Memory function is required. The core is part of the standard catalog of IP cores delivered through the CORE Generator™ at no additional cost to ISE® software customers.

关键特性

• Generates Read Only Memories (ROMs), Single- and Dual-port Random Access Memories (RAMs), and SRL16-based RAMs
• Supports data depths ranging from 16 to 65,536 words
• Supports data widths ranging from 1 to 1024 bits
• Optional registered inputs and outputs
• Use the auto-update feature in CORE Generator to convert older versions of the Distributed Memory Generator core to the latest version