3GPP Downlink Chip Rate

产品详细资料

• 3GPP 下行链路芯片速率 (PDF)
• 向Xilinx询问该核的问题

支持器件系列

• Virtex-4 FX
• Spartan-3A DSP
• Virtex-4 LX
• Virtex-4 SX
• Virtex-5 LX
• Virtex-5 LXT
• Virtex-5 SXT

The 3GPP Downlink Chip Rate LogiCORE™ IP from Xilinx® provides a Release 6 compliant, Xilinx FPGA optimized solution for Femtocell, Picocell and Macrocell solutions. The architecture has been designed to provide efficient use of FPGA logic while also offering a low bandwidth interface to an external DSP or microprocessor to reduce system level overhead using a built in OCP interface. Timing critical operations are performed by the FPGA which also simplifies the software impact with traditional DSP solutions, allowing for an optimum software/hardware balance. The core is fully optimized for speed and area whilst supporting all FDD channels.

关键特性

• Fully scalable solution to support Femtocell through to Macrocell architectures.
• Fully optimized for speed and area
• Fully synchronous design with independent interface clocks, and control interface double buffering.
• Support for all FDD channels including Scrambling, Spreading and Weighting; Slot formatting; System timing (TCELL, TDPCH, etc); Multiple sector support; Pilot Generation; Pilot, TFCI, TPC symbol insertion; STTD Encoding and a fully flexible architecture.
• Easily interfaced to external DSP or microprocessor using built-in OCP interfaces