SPI-3 Link Layer Interface, Multi-channel

器件编号:

DO-DI-POSL3MC

许可:

SignOnce

产品类型:

Core

计划:

LogiCORE

Now Supports ISE™ 9.2i

产品详细资料

文档

支持器件系列

  • Spartan-3
  • Spartan-3A DSP
  • Spartan-3E
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 SX
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-II
  • Virtex-II Pro

需求

  • ISE 9.2i Service Pack 2 or higher
  • ISE 9.2i IP Update 2

The Xilinx SPI-3 core provides a fully compliant Packet-Over-SONET/SDH (POS) solution, which can be quickly integrated into networking systems.

The Xilinx® SPI-3 Link Layer core provides a fully compliant Packet over SONET (POS) solution, which can be quickly integrated into networking systems. Through user-configurable options, such as interface width, internal Tx and Rx FIFOs, and byte or packet-level transfers, the SPI-3 core provides design flexibility while seamlessly interoperating with industry leading Application Specific Standard Products (ASSPs) to maximize the data transfer bandwidth. The Xilinx SPI-3 core is fully compliant with the Optical Internetworking Forums System Packet Interface Level 3 (SPI-3) standard (OIF-SPI3-01.0), as well as the SATURN® Development Groups POS-PHY Level 3 (PL3) interface specification.

关键特性

  • Fully compliant with OIF-SPI3-01.0 System Packet Interface Level-3 (SPI-3) standard.
  • Aggregate bandwidth in excess of 2.5-Gbps supporting OC-48 line rates and beyond.
  • Configurable interface data widths: 32-bit, 16-bit, and 8-bit.
  • Byte-Level and Packet-Level Transmit flow control options.
  • Supports 1 to 256 addressable channels.
  • Transmit and Receive cores are delivered as independent solutions for flexible implementation.
  • Fully parameterizable internal FIFO using BlockRAM, Distributed Memory, or built-in FIFO primitives.
  • Configurable Transmit Calendar implementation.
  • LocalLink User Interface allows easy interconnection.
 
 
 
 
 
职位招聘 本地活动及在线座谈 本地新闻稿 投资者关系 反馈 法律声明 Privacy Trademarks 网站地图
©  1994-2008 Xilinx, Inc. All Rights Reserved.