FIR Compiler

产品详细资料

• 向Xilinx询问该核的问题
• Release Notes (PDF)

文档

• FIR 编译器

支持器件系列

• Virtex-6
• Virtex-5
• Virtex-4
• Spartan-6
• Spartan-3A
• Spartan-3A DSP
• Spartan-3E
• Spartan-3

需求

• ISE 11.2 or higher
• ISE IP Update 11.2 or higher

The Finite Impulse Response (FIR) Filter is the one of the most ubiquitous and fundamental building blocks in DSP systems. Although its algorithm is extremely simple, the variants on the implementation specifics can be immense and a large time sink for hardware engineers today, especially in filter dominated systems like Digital Radios.

The FIR Compiler reduces filter implementation time to the push of a button, while also providing users with the ability to make trade-offs between differing hardware architectures of their FIR Filter specification.

The FIR Compiler supports three different filter architectures:

Furthermore, Virtex®-6 and Spartan®-6 performance reaches the maximum 470 MHz (-1) and 250 MHz (-2) achievable and greatly reduces the number of resources required versus lower performance FPGA devices.

New Features in v5.0 :

• Support added for Virtex-6 and Spartan-6 device families
• Leverages the pre-adder in the Virtex-6 and Spartan-6 XtremeDSP slice for symmetric filter implementation
• Extended clock and sample frequency range for Fixed Fractional Rate Decimation
• Capability added to explicitly specify hardware oversampling specification
• Capability added to enter filter coefficients as a vector directly in the CORE Generator user interface

关键特性

• Performance reaching up to 470 MHz for Virtex-6 devices (-1 speed grade)
• Performance reaching up to 250 MHz for Spartan-6 devices (-2 speed grade)
• High-performance finite impulse response (FIR), polyphase decimator, polyphase interpolator, half-band, half-band decimator, half-band interpolator, Hilbert transform, polyphase filter bank, and interpolated filter implementations
•  Multiple implementation architectures: DAFIR, Adder Tree based MACFIR (suitable for Mult18x18 enabled devices) and Adder Chain based MACFIR (suitable for XtremeDSP™ slice enabled devices)
• Supports 2-1024 taps
• Automatic control of hardware folding for the most compact implementation
• Support for up to 64 channels generally and up to 1024 for Polyphase filter bank implementations
• Interpolation and decimation factors of up to 64 generally and up to 1024 for single channel filters
• Support for Reloadable Coefficients and up to 16 coefficient sets
• Capability to share control and coefficient memory resources up to 16 parallel data paths 
• Floating Point Coefficient entry support and quantization diagnosis.
• Automatic Coefficent structure optimizations to reduce area consumed: Symmetry and Halfband
• Support for Multiple XtremeDSP slice Column Filter implementations
• Automatic selection of Block vs Distributed Memory for Data and Coefficient storage
• Instantaneous Resource Estimation of XtremeDSP slice and BRAM
• Behavioral VHDL model for fast HDL simulations
• For use with Xilinx CORE Generator™ and Xilinx System Generator for DSP