产品详细资料
文档
支持器件系列
- Virtex-5 FXT
- Virtex-5 LXT
- Virtex-5 SXT
需求
- ISE® 10.1.2
- ISE Update 10.1.2
Xilinx provides a Virtex-5 FPGA Endpoint solutions for PCI Express® to configure the Virtex-5 FPGA Built-in Endpoint Block for PCIe FPGA and includes additional logic to create a complete Endpoint solution for PCIe. This Xilinx Endpoint Block Plus Wrapper for PCIe simplifies the design process and reduces time-to-market. Many easy-to-use features and optimal configuration for Endpoint applications are available at no additional cost. This solution can be used in communication, multimedia, server and mobile platforms and enables applications such as high-end medical imaging, graphics intensive video games, DVD quality streaming video on the desktop and 10 Gigabit Ethernet interface cards. This core combined with other Xilinx connectivity solutions helps customers preserve their investment in older technologies by allowing seamless bridging to other standard and proprietary interfaces. All registered ISE users can request a license file by first registering for the wrapper (“Register”) and then accessing the lounge ( “Access Lounge”).
关键特性
- Compliant with the PCI Express Base Specification 1.1
- Fully compliant with PCI Express transaction ordering rules
- Supports maximum payload of 512 bytes
- 1 Virtual Channel
- Support lane width, x1, x4 and x8
- Bandwidth scalability interconnect width
- Pre-implemented optimal buffering for high bandwidth applications
- LocalLink User Interface for easy bridging to other Xilinx IP
- Supports removal of corrupted packets for error detection and recovery
- Uses Virtex-5 GTP/GTX Transceivers
- Design verified by a Xilinx proprietary testbench
- Tested at PCI-SIG compliance workshop and included on PCI Express Integrators List
Recommended for:
- Beginning to experienced PCI Express designers.
- Designs migrating from Xilinx Virtex-4/Virtex-II Pro using the Xilinx Endpoint LogiCORE for PCI Express (DO-DI-PCIEXP).
- Endpoint applications bridging to other cores with LocalLink.
Delivery
The Xilinx Endpoint Block Plus for PCIe is provided at no additional cost to license the wrapper to all licensed Xilinx ISE customers. The no-charge license can be obtained by first registering (“Register”) and accessing the lounge or protected area (“Access Lounge”) to request an electronic license file. The license request area, or "Lounge", is password-protected, but any licensed Xilinx ISE customers may request access to this area. By default this LogiCORE IP wrapper is shipped with a default "simulation-only" evaluation license in the standard Xilinx ISE™ software release. A separate, "full" electronic license is required to generate a bitstream for designs containing the core. The license request area, or "Lounge", is password-protected, but any licensed Xilinx ISE customers may request access to this area.
