Multiplier

文档

• Multiplier
• Multiplier

支持器件系列

• Virtex-6
• Virtex-5
• Virtex-4
• Spartan-6
• Spartan-3A
• Spartan-3A DSP
• Spartan-3E
• Spartan-3

需求

• ISE 11.3 or higher
• ISE IP Update 11.3 or higher

The multiplier operation is essential and abundant in DSP Applications. Achieving maximum implementation efficiency and clock performance is therefore critical to DSP systems and frequently presents a significant challenge to hardware engineers.

The Multiplier LogiCORE™ simplifies this challenge by abstracting away FPGA device specifics, while maintaining the required maximum performance and resource efficiency. The multiplier is able to generate parallel multipliers, and constant coefficient multipliers, both with differing implementation styles. Furthermore, with the aid of instantaneous resource estimation, hardware engineers can rapidly select the optimal solution for their system.

The latest additions to the IP provide fine control over the latency (pipelining) of the multipliers (purely combinatorial to fully pipelined) and symmetric rounding on XtremeDSP^TM  slice  based multiplication under 18 bits. Finally, fully pipelined implementations enable maximum clock frequency performance of 450 MHz and 250 MHz when DSP48 components are used in Virtex™-6 (-1) and Spartan™-6 (-2) respectively.

New Features in v11.2

• LUT based speed and area optimized implementation for Virtex-5, Virtex-6 and Spartan-6

关键特性

• 2's complement signed/unsigned fixed point multiplier
• Parallel and fixed constant coefficient multipliers
• Input data width from 2-64 bits
• Variable levels of pipelining
• Symmetric Rounding for up to 18 bit XtremeDSP Slice based multipliers
• Supports three different types of multiplier construction for Virtex-4/5 and Spartan-3A DSP Platforms: Use LUTs, Use DSP48/E and Hybrid implementation (for larger than 18-bit multipliers)
• Supports three different types of multiplier construction for Virtex-II/Spartan-3 families: Use LUTs, Use Embedded Multipliers and Hybrid implementation (for larger than 18 bit multipliers)
• Instantaneous Resource Estimation
• Optional Clock Enable, and Synchronous Clear
• VHDL behavioral models
• Instantaneous Resource Estimation
• For use with Xilinx CORE Generator™ , Xilinx AccelDSP™ Synthesis Tool, and Xilinx System Generator.