Incremental synthesis tools from Mentor Graphics combined with Xilinx incremental place and route software can reduce your design iteration time.

Many months’ worth of painstaking synthesis and place and route (PAR) iterations can be lost instantly if you need to make a functional change to your high-performance FPGA design. When ambitious performance goals come into play, achieving timing closure may involve a series of sophisticated synthesis, floorplanning, and PAR steps. Run times of design iterations may take an entire day, so complex designs requiring multiple iterations could add weeks or even months to a design schedule.

You can protect hard-fought timing gains from the disruptive effects of functional iterations through the use of a blockbased incremental design methodology. Precision™ RTL Synthesis from Mentor Graphics, used in conjunction with Xilinx ISE software, enables you to perform design iterations at the block level, thus preserving the performance of unaffected blocks. In this article, I will cover the technical details and tradeoffs of using a block-based incremental design methodology.

Incremental Synthesis Incremental synthesis gives you the ability to make an RTL code change or constraint modification that, when re-synthesized, affects only an isolated portion of your entire design hierarchy. This allows you to reuse the unaffected portion of the technology-mapped synthesis netlist, reducing synthesis runtimes as well as preserving timing on the unchanged design hierarchy.

Design Methodology Good RTL design practices can significantly improve your design’s performance.

• Functional partitioning of logic – Partition your design into major hierarchical blocks based on functionality. Although your design blocks can contain sub-hierarchies, the major design partitioning should be done at the top level of the design (Figure 1). Toplevel partitioning allows incremental synthesis results to leverage Xilinx incremental PAR techniques. Partitioning your design into groups of functionally related logic also enables the synthesis engine to more efficiently optimize critical portions of your design.
• Isolation of critical paths – Isolate critical timing paths into a single block of your design hierarchy. Incremental synthesis preserves timing on unchanged design blocks by disabling hierarchical boundary optimization on blocks that are incrementally re-synthesized. Critical timing paths routed though re-synthesized blocks may lose optimal timing.
• Registered inputs or outputs on functional blocks – Register all inputs or outputs of your major hierarchical blocks. This will minimize the effects of disabling hierarchical boundary optimization by preventing long combinatorial logic paths entering or leaving a design block.
• IOB and clock logic at the top level – Place all of your I/O logic, buffers, tristates, and clock logic (DCMs, global buffers, and such) at the top level. Instantiation of I/O buffers in a lowerlevel design block is acceptable using the Xilinx incremental PAR flow.

The bottom-up incremental flow can be divided into three steps:

1. Independent synthesis of major hierarchical blocks – Synthesize each major hierarchical block as an independent Precision RTL Synthesis project, with I/O insertion disabled. (I/O insertion will be performed later during the top-level assembly.) Precision RTL Synthesis produces both an XDB and EDIF netlist, either of which is valid when assembling the top-level design.
2. Top-level assembly – Synthesizing the top-level design stitches together all XDB or EDIF netlists from lowerlevel design blocks, performs I/O insertion, and does a complete timing characterization of the entire design. The top-level assembly project should consist of a single VHDL, Verilog™, or EDIF file that you can use to instantiate all of the lower-level design blocks. You must place DONT_TOUCH attributes on all of the lower-level design blocks before running synthesis to prevent any further optimization. The DONT_TOUCH attributes can be applied either directly in the Precision RTL Synthesis Design Hierarchy Browser (Figure 2) or as an HDL or TCL script attribute.
3. Making an incremental design change – Once you have completed and fully synthesized your design, you may wish to make HDL code or constraint modifications to fix bugs or improve performance. In a standard top-down synthesis methodology, this would require you to re-synthesize the entire design. Not only is this timeconsuming, but you may introduce timing problems into unmodified portions of your design. However, using the Precision RTL Synthesis bottom-up methodology for incremental synthesis allows you to isolate the effects of an HDL code change to specific design blocks. Should an HDL code change occur, you are only required to re-synthesize the project that references the modified HDL file. You must then, of course, run a final top-level assembly to generate a new netlist.

Incremental Place and Route Incremental synthesis helps you to reduce synthesis runtimes and preserve unmodified portions of the technology-mapped netlist. However, you must still depend on the back-end PAR tool to meet or preserve timing goals. You can use the Xilinx ISE incremental PAR flow in conjunction with the Precision RTL Synthesis incremental flow to preserve timing gains by only re-placing those design blocks that have been modified during your incremental synthesis run.

Floorplanning the Design One of the most critical steps in the Xilinx ISE incremental PAR flow is floorplanning your design. You must perform floorplanning to minimize the interconnect delay between your design blocks. You may also need floorplanning to overcome the performance limitations associated with disabling hierarchical boundary optimization during incremental synthesis. Floorplanning consists of:

• Separate area groups for each functional block – You must create a Xilinx area group for each major design block. Area groups are created and placed using the Xilinx PACE tool, which takes as its input a UCF (produced by Precision RTL Synthesis), and an NGD file produced during the translate stage (Figure 3). Area groups must not overlap, because that might adversely affect performance. Assigning nonoverlapping area groups to major hierarchical blocks allows the ISE program to completely re-place and re-route a design block inside an area group when a change is made in the netlist. If possible, you should make the area groups slightly larger than needed. This will allow successful re-placement if your design block utilization increases because of a modification. In addition to assigning area groups, you must also lock down all I/Os.
• Co-location of related blocks and I/Os – Not only is it essential to partition your design logically to optimize inter-block timing paths, but it is equally important to arrange the area groups associated with each logical partition to minimize intra-block timing paths. Area groups, as well as I/Os, that communicate with one another should be placed as close as possible to each other.

Running Place and Route

• Performing initial PAR – Once you have floorplanned your design by assigning area groups and locking down the I/Os, you must run through a first pass of technology mapping and PAR to generate an initial set of guide files (*.ngm and *.ncd). You can then use the guide files in your next PAR iteration to replace and re-route as much of your design as possible.
• Performing guided technology mapping and PAR – You can enable incremental PAR by setting the guide mode to “incremental” and specifying the guide files produced by the Xilinx technology mapper and PAR from your previous PAR iteration. The guide mode can be specified either in the ISE GUI or at the command line using the -gm switch. The Xilinx incremental guide mode directs the technology mapper and PAR to re-place and re-route all area groups and associated logic that haven’t changed, thus preserving timing gains from previous design iterations.

Conclusion Small design changes can have a devastating effect on your overall system performance, sometimes undoing months’ worth of development effort. To avoid these pitfalls, you can use Mentor Graphics Precision RTL Synthesis and Xilinx ISE PAR in tandem to implement an efficient and effective incremental design methodology that preserves timing gains and dramatically reduces your design iteration time.

To learn more about Mentor Graphics Precision RTL Synthesis, visit www.mentor.com/precision/.

For a complete description of incremental place and route, see Application Note XAPP418, “Xilinx 5.1i Incremental Design Flow” (search www.xilinx.com).

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