Xilinx and Avnet have released a new design kit that reduces time to market for a wide range of serial backplane applications.

Traditionally, designs for a variety of applications used high-speed backplanes to provide high-bandwidth communications between subsystem cards. Parallel bus implementations like PCI were popular because they offered the highest bandwidth in an industrystandard form factor.

However, for applications requiring very high bandwidth connectivity (such as telecom and networking), these parallel implementations ran into bandwidth and cost problems. Non-standard implementations were sometimes needed; these custom efforts slowed development and increased costs.

Technological advances now allow you to use high-speed serial interfaces costeffectively in chassis-based, industry-standard designs. The new Advanced Telecom Compute Architecture (ATCA™) PICMG™ 3.1 specification creates a flexible, industry-standard platform that lets you cut-and-paste previously complex and expensive high-speed serial portions of your design. This improves time to market and significantly reduces the cost normally associated with creating high-speed backplane designs.

We expect that this change will open the market to a wide range of new applications and companies that were historically shut out of these designs. Xilinx and Avnet have partnered to create a complete ATCA PICMG 3.1 Design Kit that can be used to quickly and easily implement the high-speed serial backplane portion of the ATCA PICMG 3.1 specification; it can also be used as a platform for a complete design.

PICMG 3.1 Design Kit
The card cage, shown in Figure 1, is a PICMG-standard 12U form factor sized for 16 slots in a 600 mm frame, with room for both front and rear fiber bend. The boards measure 8U x 280 mm x 1.2 in (140 in² + 4 mezzanine connectors), can run 150-200W of power, and can provide 2.4 Tbps of bandwidth. There are as many as 16 active boards per chassis. The power is at 48V and sourced from the backplane.

The main component of the ATCA PICMG 3.1 Design Kit is the line card, which is a complete development platform for creating PICMG 3.1-compliant designs. Some of the key features are:

• 15-channel, one-port full mesh fabric interface
• Intelligent Platform Management Interface (IPMI)
• Base interface ShMC port
• Headers for an application-specific personality module
• Fully distributed system management
• Management firmware running on a PowerPC™ processor
• Linux™-based control plane software.

Line Card
The Xilinx ATCA PICMG 3.1 full mesh line card (Figure 2) provides a baseline implementation of a PICMG 3.1 line card. It includes a Virtex-II Pro™ FPGA that implements both a full mesh fabric interface and a management subsystem.

The full mesh line card can serve as a development platform for PICMG 3.x line cards supporting port rates to 2.5 Gbps. It includes a Virtex-II Pro-based fabric interface that also includes all PICMG 3.0-defined card and shelf management functionalities. Management firmware executes on one of the Virtex-II Pro’s PowerPC processors running an embedded Linux operating system.

The card also includes headers to interface to a user-defined personality module. This module is used to implement application- specific line card processing and external interfaces. I/O access for this module can be reached through the front panel or rear transition modules. The personality module also has full access to the PICMG 3.1 update channel interface.

Fabric Interface FPGA
The fabric interface FPGA implements not only the data plane functions needed to transfer data across the distributed fabric, but also all management functions defined in the PICMG 3.1 specification. When placed in slots one or two, the card is capable of acting as a shelf manager.

The control plane section of the fabric interface FPGA implements management functions for the card; a block diagram for the control plane implementation is shown in Figure 3. All of these functions are implemented as firmware running on an embedded Linux operating system. The functions provided include an IPMI agent, shelf manager, and hardware and software updates via an ShMC interface.

The Virtex-II Pro FPGA includes two 400 MHz PowerPC 405 processors. One processor is used to implement management functions. It interfaces to the rest of the management subsystem by way of a 64-bit CoreConnect processor local bus and a 32-bit on-chip peripheral bus. The second PowerPC processor is available for application-specific functions.

The data plane section implements a complete 15-channel distributed switch fabric interface. The configuration shipped with the card implements a PICMG 3.1 Ethernet transport, but it can also be customized to support other PICMG 3.x transports. Figure 4 shows a block diagram of the data plane section of the fabric interface FPGA.

The Aurora interface is used to transfer packets between user-defined logic on the prototyping module and the PICMG 3.x fabric. The Aurora interface uses the fabric interface multi-gigabit transceiver signals for connectivity, but you can substitute other interfaces. For example, if you used an alternative interface such as POS-PHY Level 3, the fabric interface GPIO signals would be used for connectivity.

Conclusion
Xilinx has certified Avnet Cilicon, via the Avnet Design Services Design Centers, to sell and support the ATCA PICMG 3.1 Design Kit. The kit includes detailed design files, a comprehensive board support package, and example designs, along with test results. Design Services can be bundled along with the Design Kit to help port a custom design to the line card FPGA.

To get the most up-to-date information on the ATCA PICMG 3.1 Design Kit, visit www.avnetavenue.com and select “ATCA Design Kit.” To obtain pricing, delivery information, and a more complete description from an Avnet Cilicon representative, click on “To Register.”

Applications
The ATCA PICMG 3.1 specification defines a flexible serial backplane development platform that is applicable to a wide variety of applications. In general, the specification targets Telco carrier-grade applications, but it is also applicable to data centers and other more computationally intensive applications. Typical application areas include:
Narrowband line units Narrowband local switch line or trunk unit Digital loop carrier local terminal/ONU PBX line unit Broadband line units DSLAM Cable modem termination system/head end FTTx line unit Wireless elements Base transceiver station Base station controller Wireless access gateway Radio network controller SGSN/GGSN Home location regulator Integrated mobile switching center Service nodes Echo canceller Network resource server/intelligent peripheral Remote access server/modem pool IVR/voicemail system Core data network elements Switched LAN hub IP switch/router ATM switch Optical transport terminal	(DACS, WDM) Metro optical system Data network elements ASP server Storage area network element Compute server (thin client host, game host) Web server (e-commerce, web cache, firewall, filter) Database engine (RADIUS, LNP, billing) Video server Converged switch elements Softswitch Line access gateway Trunk access gateway Signaling gateway Internet telephony host Compression/vocoding/encryption gateway PSTN elements Universal AIN element (SCP, SCC, NCP, STP) DLC/GR-303 host terminal TDM switch core replacement PBX E.911, CALEA host Industrial applications Factory automation/robotics Multimedia studios Traffic control Military/avionics/shipboard

Printable PDF version of this article with graphics.  (3/1/04) 340 KB