| 问答编号# |
29393
|
| 型号 |
SW-Speedfiles |
| 最后更新日期 |
2009-11-03 00:00:00.0 |
| 记录状态 |
Active |
| 关键词 |
changes, updates, revised, speed, speeds, file, files, speedsfile, speedfile |
疑问描述
Keywords: changes, updates, revised, speed, speeds, file, files, speedsfile, speedfile
What is the revision history for the Spartan-3A DSP FPGA families?
解决方案
Speeds Files Revision History1.33 Release: Description and Explanation of Changes - ISE 10.1sp3 - Updated Output Adjustments for Automotive Devices (a3sd3400a and a3sd1800a)
1.32 Release: Description and Explanation of Changes - ISE 10.1sp2 - Updated maximum frequency limits for DCM
- Automotive devices: Increased delay for Input I/O Standards
- Improvements to the Timing Model for the DSP48A component
1.31 Release: Description and Explanation of Changes - ISE 10.1 - Added support for Automotive devices
- No values were changed from 1.30 to 1.31
1.30 Release: Description and Explanation of Changes - J.39 - Add support of Absolute Minimum values
- Change Status to PRODUCTION for -4 and -5 speed grade
- Updated delay values for -4 speed grade
1.29 Release: Description and Explanation of Changes - Updated values for DSP48 component for -4 and -5 speed grades
- Updated I/O Standard, block RAM, DCM, and IOB values
1.27 Release: Description and Explanation of Changes - J.32 - Updated values for DSP48
1.26 Release: Description and Explanation of Changes - Updated values for DSP48