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AR# 29942 MIG v2.0, 2.1 - Errors are encountered when synthesizing MIG Verilog output with Synplify 9.0

The following errors might occur when running a MIG output design through the Synplify 9.0 tools:

  • Errors occur during NGDBuild (Translate) due to instance names in the MIG 2.0/2.1 UCF
  • Errors occur during synthesis due to LUT6_2 black box declaration in the MIG 2.0 code

This Answer Record provides details of these errors, how to work around them, and when these issues will be fixed.

Errors During NGDBuild (Translate) Due to Instance Names in MIG UCF

Starting with Synplify version 9.0, changes were made to the way instances in "generate" blocks are named. The changes were made to comply with the 2005 LRM (Language Reference Manual) for Verilog. Because of these naming changes, the instance names in the MIG provided UCF file (which work for v8.8 and earlier) no longer exist in the EDIF file. This causes errors during NGDBuild (Translate) because the instances are notfound. This problem occurs onlywith Verilog designs as no changes have been made to the generate blocks for VHDL.

To work around this issue, the UCF must be modified to match the instance names created with Synplify 9.0. The following UCF (ML561 RDIMM) can be used as an example for changing the instance names:

http://www.xilinx.com/txpatches/pub/applications/misc/ar29942.zip

The next example shows an instance name change:

From the provided MIG 2.0 UCF:

INST "*/u_phy_calib_0/gen_gate[0].u_en_dqs_ff" LOC = SLICE_X51Y108;

To a Synplify 9.0 compatible UCF:

INST "*/u_phy_calib/genblk*.gen_gate[0].u_en_dqs_ff" LOC = SLICE_X51Y108;

This issue is resolved in MIG 2.2, which was released with ISE 10.1 Design Suite, Service Pack 1.

Errors During Synthesis Due to LUT6_2 Black Box Declaration

For Virtex-5 designs, MIG provides a black_box.v file in the generated 'rtl' directory when Synplicity and Verilog are selected in the CORE Generator project options. This file provides a black box instantiation for the LUT6_2 primitive. This was done because the Synplify versions prior to version 9.0 did not include the LUT6_2 primitive within the Xilinx libraries. Starting with Synplify 9.0, the LUT6_2 primitive is included, however, it does not match the declaration in the MIG provided black_box.v source file.

To work around this issue, remove the "black_box.v" file from the Synplify project and allow the tool to use the included LUT6_2 primitive.

This issue is resolved in MIG 2.1, which was released with ISE Design Suite 10.1.

AR# 29942
Date Created 12/13/2007
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • MIG
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