问答 #31620 - 10.1 Virtex-5 MAP - ERROR:PhysDesignRules:1242 - Invalid connection used for ILOGIC
10.1 Virtex-5 MAP - ERROR:PhysDesignRules:1242 - Invalid connection used for ILOGIC
| 问答编号# | 31620 |
| 型号 | SW-MAP |
| 最后更新日期 | 2008-09-09 00:00:00.0 |
| 记录状态 | Active |
| 关键词 | IODELAY, DDLY, D, IO,ERROR, PhysDesignRules, 1242 |
疑问描述
Keywords: IODELAY, DDLY, D, IO,ERROR, PhysDesignRules, 1242
I see the following error when data is driven from the IODELAY block to the register of an ILOGIC block:
"ERROR:PhysDesignRules:1242 - Invalid connection used for ILOGIC. The ILOGIC comp
<input_flop> D pin signal <signal_driving_flop> is not driven from an IO."
解决方案
The signal from the IDELAY block should go through the DDLY pin of the ILOGIC to drive the flip-flop, but in some cases the output of the IDELAY is being driven through the D input of the ILOGIC. But the D pin should be driven from the IO pad directly, so this is causing the Physical Design Rules check error.To work around this issue, apply the IOBDELAY constraint with a value NONE on the flop instance of the flip-flop.
Example:
INST "abc/data_in" IOBDELAY = NONE; # where abc/data_in is the input flip-flop