问答 #32441 - 11.1 Known Issue - Timing - Discrete Jitter for PLL/DCM Clock Uncertainty is pessimistic
11.1 Known Issue - Timing - Discrete Jitter for PLL/DCM Clock Uncertainty is pessimistic
| 问答编号# | 32441 |
| 型号 | SW-Timing Analyzer/TRCE |
| 最后更新日期 | 2009-04-22 00:00:00.0 |
| 记录状态 | Active |
| 关键词 | discrete, jitter, pll, dcm, clock, uncertainty, pessimistic |
疑问描述
Keywords: discrete, jitter, pll, dcm, clock, uncertainty, pessimistic
When reading the timing report, I noticed that the Clock Uncertainty associated with the PLL/DCM is pessimistic, which is caused by the Discrete Jitter also being pessimistic. Why?
解决方案
The Discrete Jitter portion of the Clock Uncertainty equation for PLL and DCM components is very conservative. The actual values from characterization are approximately 30% less than the reported values in the timing report.This is scheduled to be fixed in the next quarterly update or major release of the speed files.