| 问答编号# | 32482 |
| 专题 | SW-PlanAhead |
| 最后更新日期 | 2009-04-20 00:00:00.0 |
| 记录状态 | Active |
| 器件 | - |
| 设计工具 | - |
| IP | - |
| 开发板与电缆 | - |
Keywords: GCLK, BUFG, global, IBUFG, negative, GC, CC
I accidentally constrained my single-ended clock to the N side of a Global Clock differential pair.
Why did PlanAhead allow me constrain the clock to this location, and why did DRC not report it?