| 问答编号# |
32543
|
| 型号 |
SW-Timing Analyzer/TRCE |
| 最后更新日期 |
2009-06-05 00:00:00.0 |
| 记录状态 |
Active |
| 关键词 |
local inversion, wrong, analyze, analyses, inverted, 180, degree |
疑问描述
Keywords: local inversion, wrong, analyze, analyses, inverted, 180, degree
Timing analysis is being performed on an incorrect clock edge. My design is using an INV or a BUFIO2 to perform the clock inversion.
How can I correct the analysis?
解决方案
When using logic such as a LUT (INV) or even a BUFIO2 to invert a clock, the timing engine has no indication that the clock was inverted. The inverting components are viewed as combinatorial logic, not clock-modifying blocks.
To correct this issue, use local inversion or a clock-modifying block to invert the clock.
DCM, DLL, PLL, BUFR, PMCD, and MMCM components are considered to be clock-modifying blocks.