问答 #32632 - SPI-4.2 v9.1- "ERROR:Place:909 - Regional Clock Net "core_pl4_src_top0/tsclk_gp" cannot possibly be routed..." message during Map for Source core
SPI-4.2 v9.1- "ERROR:Place:909 - Regional Clock Net "core_pl4_src_top0/tsclk_gp" cannot possibly be routed..." message during Map for Source core
| 问答编号# | 32632 |
| 型号 | IP-Telecom-SPI-4.2 |
| 最后更新日期 | 2009-05-04 00:00:00.0 |
| 记录状态 | Active |
| 关键词 | CORE, Generator, PL4, packet, SONET, oif, open, physical, link, layer, source, synchronous, phase, alignment, sink, dynamic, static, dpa, spi4.2, spi4-2, Virtex-4, Virtex-5 |
疑问描述
Keywords: CORE, Generator, PL4, packet, SONET, oif, open, physical, link, layer, source, synchronous, phase, alignment, sink, dynamic, static, dpa, spi4.2, spi4-2, Virtex-4, Virtex-5
The SPI-4.2 Source core in some cases might fail Map with the following error:
ERROR:Place:909 - Regional Clock Net "core_pl4_src_top0/tsclk_gp" cannot possibly be routed to component "core_pl4_src_top0/U0/cal0/TStat_d1<0>" (placed in clock region "CLOCKREGIONP_X1Y4"), since it is too far away from source BUFR "core_pl4_src_top0/U0/clk0/tsbr" (placed in clock region "CLOCKREGION_X1Y0").
解决方案
This is a Map tool issue where Map is not able to place a TStat* pin in a bank that can be reached by the BUFR clock.One possible work-around is to manually place the BUFR component to an appropriate location relative to the TStat pins.
Alternatively, the TStat* pins can be manually placed in a bank reachable by the BUFR being used by the tools. This can be added as a constraint to the UCF. For example:
INST "TStat*" LOC = "Bank14";
Revision History
05/04/2009 - Initial Release