问答 #33021 - 11.2 Virtex-6 Place - Designs with very low utilization may have very poor QOR
11.2 Virtex-6 Place - Designs with very low utilization may have very poor QOR
| 问答编号# | 33021 |
| 型号 | SW-Place |
| 最后更新日期 | 2009-06-23 00:00:00.0 |
| 记录状态 | Active |
| 关键词 | QOR, low, utilization |
疑问描述
Keywords: QOR, low, utilization
My design is very small, but it failed to route successfully. When I examined the placement in FPGA Editor, I can see that the placement is very congested. Is this a known problem?
解决方案
While there have been some improvements for ISE 11.2 since the beta release for Virtex-6, there are still some issues with the quality of placement results for very low utilization designs. Some special placement algorithms are used to handle such designs and this sometimes causes problems. In one case, a single module was implemented with an Area Group Range that restricted the placement to a small but sufficient area of the device. The placement results for this implementation were very poor with many timing errors. When the low utilization algorithms were disabled, the timing results improved dramatically.The following variable can be tried in the case where the QOR are suspect for a low utilization design:
Linux
setenv PAR_USE_LOWUTILHEUR 0
Windows
SET PAR_USE_LOWUTILHEUR=0
For general information about setting ISE environment variables, see (Xilinx Answer 11630).