问答 #33113 - 11.2 Timing Analyzer - Autogenerated constraints report incorrect value for clk to pad
11.2 Timing Analyzer - Autogenerated constraints report incorrect value for clk to pad
| 问答编号# | 33113 |
| 型号 | SW-Timing Analyzer/TRCE |
| 最后更新日期 | 2009-08-06 00:00:00.0 |
| 记录状态 | Active |
| 关键词 | Timing, Analyzer, Autogenerated, incorrect, Virtex5, Virtex-5 |
疑问描述
Keywords: Timing, Analyzer, Autogenerated, incorrect, Virtex5, Virtex-5
When trying to analyze the design against Auto-generated timing constraints for a Virtex-5 design, I find that the clk to pad value in the data sheet report is incorrectly reported.
Is this a known issue?