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AR# 33256

LogiCORE IP Video Direct Memory Access (VDMA) - Release Notes

描述

This Answer Record contains the Release Notes and Known Issues list for the CORE Generator LogiCORE IP Video Direct Memory Access (VDMA) Core.

The following information is listed for each version of the core:
  • New Features
  • Bug Fixes
  • Known Issues
LogiCORE IP Video Direct Memory Access (VDMA):
http://www.xilinx.com/products/ipcenter/EF-DI-VID-DMA.htm

解决方案

General LogiCORE IP Video Direct Memory Access (VDMA) Issues

LogiCORE IP Video Direct Memory Access (VDMA) v1.1

There was a v1.1 rev1 patch available in (Xilinx Answer 35229). This patch was intended to fix issues listed below as:
(Xilinx Answer 38718)and (Xilinx Answer 38719).
  • Initial Release in ISE 12.3 software
New Features
  • Added Read_Write mode which allows bidirectional data transfers
Bug Fixes
  • (Xilinx Answer 35040)Why is the control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6 FPGA?
Known Issues
  • (Xilinx Answer 33398)Why do I receive a warning about a missing top level when generating the EDK Pcore interface?
  • (Xilinx Answer 38718)Why is the VDMA so large when using the pCore interface?
  • (Xilinx Answer 38719) Why does the pCore driver always reset both the read and the write sides of the bi-directional interface?
LogiCORE IP Video Direct Memory Access (VDMA) v1.0
  • Initial Release in ISE 11.3software
New Features
  • Initial release
Bug Fixes
  • N/A
Known Issues
  • (Xilinx Answer 33398)Why do I receive a warning about a missing top level when generating the EDK Pcore interface?
  • (Xilinx Answer 35040)Why is the control register in big endian format, instead of little endian format as documented in the data sheet when targeting Spartan-6 or Virtex-6 FPGA?

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AR# 33256
日期 05/20/2012
状态 Archive
Type 版本说明
IP
  • Video DMA
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