问答 #33282 - Spartan-6 FPGA - Speed Files Revision History

问答编号#	33282
型号	SW-Speedfiles
最后更新日期	2009-11-18 00:00:00.0
记录状态	Active
关键词	changes, updates, new, current, revised, release, speeds, file

解决方案

Speed Files Revision History

1.03 Release: Description and Explanation of Changes - 11.4
General Devices
+ DSP - updated setup/hold parameters for -2 and -4
+ PCIe - updated parameters
+ IOB - updated parameters
+ GTP - updated parameters

1.02 Release: Description and Explanation of Changes - 11.4
General Devices
+ Add automotive subfamily for -2 and -3 speed grades
+ CLB - Updated equations for MINPERIODs
+ DSP - Updated MINPERIOD/FMAX for -2 and -3 speed grades
+ IOB - Updated equations for MINPERIODs - updated -3 speed grade for ILOGIC/OLOGIC delays for simulation - Updated TFF delays for DDR
+ IODELAY - Updated setup/hold for -3 and -4 speed grades
+ SERDES - Updated setup/hold for -3 and -4 speed grades
+ DCM - Updated Pulsewicth parameters and Jitter values
+ GTP - Updated parameters
+ PCIe - Updated derate factors
+ MCB - Updated parameters

LP Devices
+ Updates to the IODELAY, SERDES, DSP, GTP, and clocking components
+ Fixed Negative data valid window for simulation
+ DCM - Updated Pulsewicth parameters and Jitter values
+ IOB - Updated TFF delays for DDR
+ DSP - Updated parameters
+ CLB - Updated equations for MINPERIOD
+ GTP - Updated parameters
+ PCIe - Updated derate factors
+ MCB - Updated parameters

1.01 Release: Description and Explanation of Changes - 11.3
+ Added support for 6slx75(t)
+ DCM - Updated DCM_OFFSET values. This makes the min bigger than the max (on purpose) to prevent negative setup and hold windows on downstream blocks.
+ DSP - For existing paths that use OPMODE6 or generic OPMODEs that include B1REG, a pre-adder delay was added. - There were more parameters that were added to reduce the delay when the pre-adder is specifically turned off.
+ Interconnect - Added new speed models for input path from pad to IOI.
+ PLL - Updated PLL_OFFSET values. This makes the min bigger than the max (on purpose) to prevent negative setup and hold windows on downstream blocks. - Set system synchronous setting set to tap value 0. This was based off silicon characterization.
+ BRAM - Differentiated between setup / hold and recovery / removal checks when in synchronous and asynchronous reset mode.
+ IO / Clocking - Updated O_BUFIO2.drive from matching clk tree simulations - Updates to IO and clocking models BSW_IOBUF_MUX,BSW_TERM_CLK,BSW_TERM_CLK2 - Updated B_IOCLK_TB/LR for sa16 and sa45 - Updated BSW_REGC_CLK_MUX_2 from design
+ Updated IOB, clocking components
+ BRAM/DSP - Updated input pin delays
+ GTP - Added data sheet parameters and MINPERIOD values for D_GTPA1_DUAL_{GCLK??,PLLCLK??}_REFCLKPLL
+ PCIe - Updated values for -3 speed grade
+ SERDES - Updated values