问答 #33312 - Serial RapidIO v5.4 - Release Notes and Known Issues for ISE software 11.3

问答编号#	33312
型号	IP-RapidIO-Serial
最后更新日期	2009-11-19 00:00:00.0
记录状态	Active
关键词	Endpoint, high, speed, high-speed, PHY, logical, design environment, SRIO, RIO, rapid, IO, MGT, 11.1, I/O, CORE Generator, physical, logicalio, transport, buffer, mgt, vio, xviodemo

解决方案

New Features

- ISE 11.3 Support
- Spartan-6 FPGA Verilog support
- Updated Virtex-6 FPGA functionality for initial board bring-up

Resolved Issues in v5.4

(Xilinx Answer 33193) Virtex-6 FPGA 1.25 Gbs simulations fail because the MMCM_ADV UniSim Model does not handle fractional values correctly
-CR# 527725

(Xilinx Answer 33194) Virtex-6 FPGA comma alignment set to align on even byte boundaries only
-CR# 525309

(Xilinx Answer 32122) Re-Transmit Suppression Support bit set incorrectly as 1'b0
- CR# 507334

(Xilinx Answer 33454) Virtex-6 FPGA bring-up issues (pending further testing)
- Using integer values for the MMCM_ADV, regenerated Virtex-6 FPGA wrappers based on general hardware characterization results, revised reset sequence.
- CR#527725, CR#525309, CR#531695
- See linked Answer Record 33454 for further updates as hardware validation progresses.

- GUI settings incorrect or not properly reflected in hardware.
- The following register fields were corrected: Re-transmit Suppression Mask, Logical Layer Extended Features Pointer, Device Vendor ID.
- CR#528369, CR#528370

Known Issues in v5.4

- Virtex-6 and Spartan-6 FPGA solutions are pending hardware validation.

- (Xilinx Answer 33574) Recommended modifications to Example Design reset scheme
- Version to be fixed: v5.5
- CR# 533208, 533209, 533212

- (Xilinx Answer 33527) Example design "implement.bat" file has error
- Version to be fixed: v5.5
- CR# 533796

- (Xilinx Answer 33528) ISE software GUI does not recognize certain core constraints
- Version to be fixed: v5.5

- (Xilinx Answer 33453) VHDL example design simulation error when CRF bit de-selected
- Version to be fixed: v5.5
- CR# 532020

- (Xilinx Answer 33447) VHDL example design simulation error with core_clk.vhd
- Version to be fixed: v5.5
- CR# 532098

- (Xilinx Answer 32614) PHY does not pass CRF bit correctly on RX frames
- Version to be fixed: v5.5
- CR# 519603

- (Xilinx Answer 32195) Virtex-4 FXT FPGA 3.125G, 4x Core might not meet timing
- Version to be fixed: v5.5
- CR# 506364

- (Xilinx Answer 32188) Virtex-5 FXT FPGA Core might show data errors and "input-error stopped" state
- Version to be fixed: v5.5
- CR# 510781 - Virtex-5 GTX FPGA clock compensation logic might corrupt post 8b/10b data.

- (Xilinx Answer 32316) If 16-bit Device IDs are used, treq_vld_n can assert before treq_sof_n on an SWRITE
- Version to be fixed: Fix Not Scheduled
- CR# 514611

- (Xilinx Answer 30023) Virtex-4, Virtex-5 LXT/SXT, and Virtex-5 FXT FPGA core configurations are unable to train down to x1 mode in Lane 2. Traindown in Lane 0 works successfully, but the Virtex-4, Virtex-5 LXT/SXT, and Virtex-5 FXT FPGA configurations are unable to Traindown in Lane 2. The RocketIO transceivers only allow Traindown to the channel bonding master.
- Version to be fixed: Fix Not Scheduled
- CR# 457109.

- (Xilinx Answer 30021) Core reinitialization during error recovery causes recoverable protocol error. This is a corner condition that could occur if the core is forced to reinitialize (i.e., - force_reinit) while it is in the process of error recovery. If this condition occurs, packets will be sent during recovery's quiet period. This situation is recoverable.
- Version to be fixed: Fix Not Scheduled
- CR# 457885

- (Xilinx Answer 29522) Post-Synplicity synthesis implementation runs might exhibit UCF failures. Synplicity generated net names are not consistent with XST generated names and might not be consistent between core types. The ".ucf" file must be edited in these failure cases.
- Version to be fixed: Fix Not Scheduled
- CR# 447782

- (Xilinx Answer 24982) PNA cause field might occasionally reflect a reserved value. The cause field is for debug purposes only and will not affect functionality. Occurrence is rare and requires alignment of multiple control symbols.
- Version to be fixed: Fix Not Scheduled
- CR# 436767

(Xilinx Answer 24970) Control Symbols might be lost on reinit. This is an unusual and ultimately recoverable error. Set the Additional Link Request Before Fatal value on the Physical Configuration page of the GUI to "4" in order to prevent a lost Link Request or Link Response from causing the core to enter the port error state.
- Version to be fixed: Fix Not Scheduled
- CR# 436768

(Xilinx Answer 24968) Logical Rx does not support core side stalls. The Rx buffer must provide packets to the logical layer without buffer induced stall cycles. The buffer reference design provided with the core is a store and forward buffer and complies with this rule.
- Version to be fixed: Fix Not Scheduled
- CR# 436770


Revision History
09/16/2009 - Initial Release
09/17/2009 - Added ARs 33527 and 33528 to Known Issues
11/04/2009 - Removed AR 32063 from Known Issues. Common Clock mode no longer available.
11/18/2009 - Added AR 33574 to Known Issues