问答 #33362 - Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.3 - "Warning:Par:468 - Your design did not meet timing" seen in some configurations
Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.3 - "Warning:Par:468 - Your design did not meet timing" seen in some configurations
| 问答编号# | 33362 |
| 型号 | IP-DS-Embedded Tri-Mode EMAC |
| 最后更新日期 | 2009-08-31 00:00:00.0 |
| 记录状态 | Active |
| 关键词 | TEMAC, EMAC, hard TEMAC, failure, timing |
疑问描述
Keywords: TEMAC, EMAC, hard TEMAC, failure, timing
For a small number of configurations, the example designed provided with v6_emac_v1_3 may not achieve timing closure. This is primarily due to poor placement of logic during the ISE tool flow.
解决方案
The example design can be constrained within an area group to ensure better logic placement. While the hard TEMAC macro is already constrained by the UCF to the right side of the die, ensuring that the remaining logic is also placed on right side of the die results in more reliable timing closure.This solution may not be necessary, or may require modification, when the example design is not used in isolation.
Add the following constraint to the provided UCF:
For LXT and SXT devices:
INST "*" AREA_GROUP = "AG_example_design";
AREA_GROUP "AG_example_design" RANGE = CLOCKREGION_X1Y0:CLOCKREGION_X1Y3;
For HXT devices:
INST "*" AREA_GROUP = "AG_example_design";
AREA_GROUP "AG_example_design" RANGE = CLOCKREGION_X1Y4:CLOCKREGION_X1Y7;