问答 #33741 - MIG v3.2, v3.3, Virtex-4/Virtex-5 FPGA DDR/DDR2 - The timing spreadsheet provided to calculate timing margin before and after DQS incorrectly only accounts for Tstaphaoffset in the "Before DQS" column

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MIG v3.2, v3.3, Virtex-4/Virtex-5 FPGA DDR/DDR2 - The timing spreadsheet provided to calculate timing margin before and after DQS incorrectly only accounts for Tstaphaoffset in the "Before DQS" column

问答编号#	33741
型号	IP-MIG-DDR SDRAM
最后更新日期	2009-11-17 00:00:00.0
记录状态	Active
关键词	spreadsheet, xls, Memory Interface Generator, window, PLL, clk0, clk90

疑问描述

Keywords: spreadsheet, xls, Memory Interface Generator, window, PLL, clk0, clk90

The timing spreadsheet provided to calculate timing margin before and after DQS incorrectly only accounts for Tstaphaoffset in the "Before DQS" column.

解决方案

The timing parameter for the PLL static offset, Tstaphaoffset, should be accounted for in both the Before and After DQS column of the spreadsheet write_data_timing.xls. In MIG 3.2, this parameter is only accounted for in the "Before DQS" column, while the "After DQS" column lists it's contribution as 0ps.

This issue is to be fixed in a future release of MIG. For now, you must manually update the spreadsheet to use the same value listed in the "Before DQS" column in the "After DQS" column for the parameter Tstaphaoffset.