问答 #33761 - Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - How to Enable use of a 100 MHz Reference Clock
Spartan-6 FPGA Integrated Block Wrapper v1.2 for PCI Express - How to Enable use of a 100 MHz Reference Clock
| 问答编号# | 33761 |
| 型号 | IP-SysIO-PCI Express Block |
| 最后更新日期 | 2009-11-11 00:00:00.0 |
| 记录状态 | Active |
| 关键词 | PCIe, S6 |
疑问描述
Keywords: PCIe, S6
The v1.2 release allows the use of a 125 MHz reference clock. A 100 MHz reference clock is also supported.
解决方案
Enabling the use of a 100 MHz reference clock requires some modification to the generated wrapper files. This requirement will go away in the v1.3 release coming in ISE software 12.1. The parameters to change are similar in both VHDL and Verilog.In the file source/<core_name>.v[hd], change the generic[VHDL] or parameter[Verilog] REF_CLK_FREQ to 0.
In the file source/gtpa1_dual_wrapper_tile.vhd, change the following attributes:
(Change _0 to _1 based on channel used)
CLK25_DIVIDER_0 to 4
PLL_DIVSEL_FB_0 to 5
PLL_DIVSEL_REF_0 to 2
To use a 100 MHz reference clock, the v1.2 release must be used; it is not supported with v1.1.
For more information about clocking Xilinx devices for PCI Express, see (Xilinx Answer 18329).
Revision History
11/11/2009 - Fixed PLL_DIVSEL_REF_0 value. Should be 2 not 0.
11/05/2009 - Initial Release