问答 #33803 - MIG v3.3, Virtex-6 FPGA, DDR2/DDR3 - Read Modify Write command fails when using Data Mask to mask individual bytes
MIG v3.3, Virtex-6 FPGA, DDR2/DDR3 - Read Modify Write command fails when using Data Mask to mask individual bytes
| 问答编号# | 33803 |
| 专题 | IP-MIG-DDR3 SDRAM |
| 最后更新日期 | 2009-11-16 00:00:00.0 |
| 记录状态 | Active |
| 器件 | - |
| 设计工具 | - |
| IP | - |
| 开发板与电缆 | - |
疑问描述
Keywords: DDR2, DDR3, Read Modify Write, RMW
The MIG v3.3 Virtex-6 FPGA DDR2/DDR3 designs support Read Modify Write commands. When a Read Modify Write is performed in conjunction with a partial data mask, the modified data is not written to the memory.
解决方案
This is a known issue with MIG v3.3 which affects both simulation and hardware. To avoid this issue, Read Modify Write commands should not be performed with a partial data mask.This issue is scheduled to be resolved in the next version of MIG (released with ISE Design Suite 12.1).