问答 #33830 - LogiCORE IP Video Timing Controller v2.0 - Mismatch between the behavioral simulation and the post-implementation gate level simulation results when using the default GUI values for Max Clock Per Line and the Max Lines Per Frame
LogiCORE IP Video Timing Controller v2.0 - Mismatch between the behavioral simulation and the post-implementation gate level simulation results when using the default GUI values for Max Clock Per Line and the Max Lines Per Frame
| 问答编号# | 33830 |
| 专题 | IP-DSP MVI |
| 最后更新日期 | 2009-11-18 00:00:00.0 |
| 记录状态 | Active |
| 器件 | - |
| 设计工具 | - |
| IP | - |
| 开发板与电缆 | - |
疑问描述
Keywords: ISE, display, hsync, vsync, horizontal, vertical, sync
Why do I see a mismatch between the behavioral simulation and the post-implementation gate level simulation results when I use the default GUI Values for Max Clock Per Line and the Max Lines Per Frame?
解决方案
To ensure that the behavioral simulation and the post-implementation simulation always match, set the Max Clock Per Line and the Max Lines Per Frame to exactly 4095.For a detailed list of LogiCORE IP Video Timing Controller Release Notes and Known Issues, see (Xilinx Answer 32754).