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AR# 34396

MIG 7 Series and Virtex-6 DDR2/DDR3 - JEDEC Specification Self-Refresh


This section of the MIG Design Assistant focuses on the Self Refresh Operation, defined by the JEDEC Specification,as it applies to the MIG 7 series and Virtex-6 DDR2 and DDR3 designs.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


The self refresh operation is defined in section 4.10 of JEDEC Specification JESD79-2 DDR3 SDRAM Standard and 2.10 of Specification JESD79-3 DDR2 SDRAM Standard and can be used to save power by powering down the memory controller and putting the memory into a self refresh state.

This feature is not supported by the MIG 7 series or MIG Virtex-6 DDR2/DDR3 controller. For low power applications the Spartan-6 device and memory controller, which does support Self-Refresh, might be more suitable.

The MIG 7 Series IP does support usage of the IOBUFDS_DCIEN and IOBUFDS_INTERMDISABLE primitives which disable portions of the IO during idle periods to save power. Please see the 7 Series FPGAs SelectIO Resources User Guide for detailed information on these primitives.

NOTE: For information on how Auto-Refresh is used with the MIG 7 Series and Virtex-6 DDR2/DDR3 controller, see (Xilinx Answer 34371).



Answer Number 问答标题 问题版本 已解决问题的版本
34359 MIG Virtex-6 and 7 Series DDR3 - Jedec Specification - Multi-Purpose Register N/A N/A
51684 MIG 7 系列 DDR2/DDR3 - JEDEC 规范 N/A N/A


Answer Number 问答标题 问题版本 已解决问题的版本
34330 MIG Virtex-6 DDR2/DDR3 - JEDEC Specification N/A N/A
40519 Serial RapidIO v5.6 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
AR# 34396
日期 01/29/2013
状态 Active
Type 解决方案中心
  • Virtex-6 CXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • MIG