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Xilinx Virtex-6 FPGA Solution Center

The Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices. Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.

设计助手

Xilinx Virtex-6 FPGA Solution Center - Design Assistant

The Virtex-6 FPGA Design Assistant walks you through the recommended design flow for Virtex-6 FPGA while debugging commonly encountered issues for clocking, fabric, and block RAM/FIFO design. The Design Assistant not only provides useful design and troubleshoot information, but also points you to the exact documentation you need to help you design efficiently with Virtex-6 FPGA.

NOTE: This answer record is part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963). The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices. Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.


First, select the design phase where you have a question or are troubleshooting an issue related to your Virtex-6 FPGA design. This ensures the Design Assistant points you to the information you need to move forward with your design.

(Xilinx Answer 34965) - Getting Started with the Virtex-6 FPGA
(Xilinx Answer 34977) - Designing for the Virtex-6 FPGA
(Xilinx Answer 37710) - Board Level Considerations
(Xilinx Answer 37211) - Troubleshooting - Clocking, Fabric, block RAM/FIFO

* For troubleshooting of other areas of FPGA design, please see the Top Issues and Design Assistant areas of other available solutions centers.


技术文档

Virtex-6 FPGA Documentation - What documentation should I review to find out if the Virtex-6 FPGA features and specifications are right for my system?

What Xilinx documentation should I review to help me understand whether the Virtex-6 FPGA specifications and features are right for my system?

NOTE: This answer record is part of the Xilinx Virtex-6 Solution Center (Xilinx Answer 34963). The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices. Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.


The Xilinx Documentation Center contains all Virtex-6 FPGA related documentation:
http://www.xilinx.com/support/documentation/virtex-6.htm

The following documents are available:

  • Virtex-6 Family Overview
  • Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
  • Virtex-6 Errata
  • Virtex-6 User Guides

Use the Virtex-6 Family Overview to understand the features available in the Virtex-6 FPGA device family and view the differences among the devices within the Virtex-6 FPGA family to assist in product selection.

Use the Virtex-6 FPGA Data Sheet to review the DC and Switching Characteristic specifications for the Virtex-6 family.

Review the Virtex-6 Errata to determine whether the device you are considering has any exceptions to data sheet specifications.

Review the Virtex-6 User Guides to understand usage details for the Virtex-6 FPGA resources.


设计咨询

有关 Virtex-6 FPGA 设计咨询的主要答复记录

针对一般设计过程出现的重大问题创建设计咨询答复记录,精选后用于 Xilinx 提醒通知系统。

该设计咨询涵盖 Virtex-6 FPGA 以及影响 Virtex-6 FPGA 设计的相关问题。


2013 年 4 月 8 日发布的设计咨询提醒:
04/05/2013 (Xilinx 答复 45166) 更新有关 Virtex-6 FPGA GTH 收发器的设计咨询,包含更新的 RX_P1_CTRL 属性值

2012 年 8月 13 日发布的设计咨询提醒:
08/15/2012 (Xilinx 答复 51145) 设计咨询 - 14.2 iMPACT - 对 Virtex-6 进行间接编程导致工具在无预警的情况下崩溃

2012 年 5月 21 日发布的设计咨询提醒:
05/17/2012 (Xilinx 答复 47938) 有关 Virtex-6 FPGA 的设计咨询 - 使用 OPAD Tioop/Tiotp 的设计必须通过时序分析重新运行

2012 年 2 月 13 日 发布的设计咨询提醒:
01/25/2012 更新至(Xilinx 答复 42444) Virtex-6 FPGA 设计咨询 - 使用 18K/36K block RAM 或 18K/36K FIFO 的设计必须通过时序分析来重新运行

2012 年 1月 16 日 发布的设计咨询提醒:
01/13/2012 (Xilinx 答复 45166) 有关 Virtex-6 GTH 收发器的设计咨询- 启动时出现错误/ RXRECCLK 在启动时未切换

2011 年 12月 19 日 发布的设计咨询提醒:
12/13/2011(Xilinx 答复 43591)有关Virtex-6 FPGA GTH 收发器的设计咨询 - 有关RXBUFRESET的初始化顺序及 BUFFER_CONFIG_LANEx 问题,在 ES Silicon 中包含修补信息

设计咨询提醒(2011 年 11 月 21 日)
11/21/2011 - (Xilinx 答复 44174) 有关启动后正确同步触发器和 SRL 的技术设计咨询

2011年9月19日发布的设计咨询提醒:
09/19/2011(Xilinx 答复 43829)有关Virtex-6 FPGA GTH 收发器的设计咨询: 在x4 模式封装中错误的 RXBUFRESET 连接

2011年8月22日发布的设计咨询提醒:
08/22/2011(Xilinx 答复 43591)Virtex-6 FPGA GTH 收发器设计咨询 - 解决 RXBUFRESET 相关的初始化序列以及 BUFFER_CONFIG_LANEx 问题所需的更新

2011 年 8 月 8 日发布的设计咨询提醒:
08/08/2011(Xilinx 答复 43346) Virtex-6 FPGA 设计咨询 - 关于 GTH 收发器非重定时 10G+ 光学接口(如 SFP+ 和 QSFP)的建议
08/08/2011 (Xilinx 答复 42682)Virtex-6 FPGA 设计咨询 - 当目标 FPGA 不是 JTAG 链中的唯一器件时,13.x iMPACT - eFUSE 密钥编程出现错误

2011 年 7 月 11 日 发布的设计咨询提醒:
07/08/2011 (Xilinx 答复 42444) Virtex-6 FPGA 设计咨询 - 使用 18K/36K block RAM 或 18K/36K FIFO 的设计必须通过时序分析来重新运行
07/07/2011 (Xilinx 答复 41821) Virtex-6 FPGA 设计咨询 - BitGen Option -g Next_Config_Addr:默认值已更改
07/07/2011 (Xilinx 答复 41099)Virtex-6 FPGA 设计咨询 - 同步 FIFO 必须让复位同步到 RDCLK/WRCLK

2011 年 7 月 6 日 发布的设计咨询提醒:
07/01/2011 (Xilinx 答复 42444) Virtex-6 FPGA 设计咨询- 使用 18K/36K block RAM 或 18K FIFO 的设计必须通过时序分析来重新运行
06/30/2011 (Xilinx 答复 42682)Virtex-6 FPGA 设计咨询 - 当目标 FPGA 不是 JTAG 链中的唯一器件时,13.x iMPACT - eFUSE 关键编程出错
04/11/2011 (Xilinx 答复 41099) Virtex-6 FPGA 设计咨询 - 同步 FIFO 必须让复位同步到 RDCLK/WRCLK

2011 年 3 月 21 日发布的设计咨询提醒:
03/18/2011 (Xilinx 答复 40885) Virtex-6 FPGA 设计咨询更新:量产 GTH 收发器包括 GTH TXUSERCLKOUT/RXUSERCLKOUT 操作指南

2011 年 3 月 7 日发布的设计咨询提醒:
03/04/2011 (Xilinx 答复 40885) 有关 Virtex-6 FPGA 的设计咨询 - 量产 GTH 收发器

2010 年 10 月 18 日发布的设计咨询提醒:
10/11/2010 (Xilinx 答复 38132) Virtex-6 FPGA MMCM 设计咨询 - MMCM BANDWIDTH 属性要求
10/11/2010 (Xilinx 答复 38133) Virtex-6 FPGA MMCM 设计咨询 - 当 Fclkin > 315 MHz 时,DIVCLK_DIVIDE 值的限制
09/27/2010 (Xilinx 答复 38134) Virtex-6 配置 - PROGRAM_B 引脚加电前为低电平并不延误配置
09/07/2010 (Xilinx 答复 36642) Virtex-6 系统监控器 - DCLK 的最大频率调低至 80MHz

2010 年 8 月 30 日发布的设计咨询提醒:
08/27/2010 (Xilinx Answer 37667) Virtex-6 FPGA -1L 工业级电压输入规范修改

2010 年 3 月 22 日发布的设计咨询提醒:
03/19/2010 (Xilinx 答复 34859) Virtex-6 FPGA Block RAM 设计咨询 - 地址空间部分重叠
02/11/2010 (Xilinx 答复 33849) Virtex-6 FPGA MMCM - 对所有 MMCM、VCO 最小频率和 CLKBOUT_MULT_F 值的新要求
01/22/2010 (Xilinx 答复34164) Virtex-6 11.4 ISE - Virtex-6 FPGA 设计必须在 ISE 11.5 或更高版本的软件重新运行直至实现

修订历史:

04/05/2013 - 更新答复记录 45166
09/24/2012 - 略有改动; 内容无改动
08/09/2012 - 新增答复记录 51145
05/17/2012 - 新增答复记录 47938
02/13/2012 -新增答复记录更新 42444
01/13/2012 - 新增答复记录 45166
12/13/2011 - 更新答复记录 43591
12/12/2011 - 更新 44174 标题
11/21/2011 - 新增答复记录 44174
09/15/2011 - 新增答复记录 43829
08/18/2011 - 新增答复记录 43591
08/01/2011 - 新增答复记录 43346, 更新答复记录 42682
07/07/2011 - 新增答复记录 41821, 更新答复记录 42444 和 41099
07/05/2011 - 新增答复记录 42444, 更新答复记录 41099
06/30/2011 - 新增答复记录 42682
03/18/2011 - 更新答复记录 40885
03/04/2011 - 新增答复记录 40885
10/14/2010 - 新增答复记录 38134, 36642
10/12/2010 - 新增答复记录 38132、 38133
08/27/2010 - 新增答复记录 37667
03/19/2010 - 初始版本


Answer Number 问答标题 问题版本 已解决问题的版本
45166 Virtex-6 FPGA GTH 收发器 - 信道处于节能模式会导致Quad出现错误 N/A N/A
43829 Design Advisory for Virtex-6 FPGA GTH Transceivers - Incorrect RXBUFRESET connections in the wrapper in x4 mode N/A N/A
41821 Design Advisory for Virtex-6 BitGen Option Change Can Cause Configuration Failures for Bit Files Generated in 13.2 Where 13.1 Files Worked N/A N/A
41099 Design Advisory for Virtex-6 FPGA - Synchronous FIFOs must have reset synchronized to RDCLK/WRCLK N/A N/A
38134 Design Advisory for Virtex-6 Configuration - PROGRAM_B pin held Low prior to power up does not delay configuration N/A N/A
38133 Virtex-6 FPGA MMCM 设计建议- 当 Fclkin > 315 MHz 时限定 DIVCLK_DIVIDE 的值 N/A N/A
38132 Virtex-6 FPGA MMCM 设计咨询 - MMCM BANDWIDTH 属性要求 N/A N/A
37667 Virtex-6 FPGA -1L 工业级 Vccint 规范修改 N/A N/A
34859 Virtex-6 FPGA Block RAM 设计咨询 - 地址空间重叠 N/A N/A
47938 有关 14.1 时序分析 Virtex-6 的设计咨询——Tioop/Tiotp 值在分析 OFFSET OUT 和 FROM:TO 约束时有所增加 N/A N/A
44174 设计咨询 - 在启动后正确同步化SRL与触发器的技巧 N/A N/A
33849 Virtex-6 FPGA MMCM - New Requirements for all MMCMs, VCO minimum frequency, and CLKFBOUT_MULT_F values N/A N/A
34164 Virtex-6 11.4 ISE - Virtex-6 FPGA designs must be re-run through implementation in ISE 11.5 or later software N/A N/A
51145 设计咨询 - 14.2 iMPACT - 对 Virtex-6 进行间接编程导致工具在无预警的情况下崩溃 N/A N/A

常见问题

Virtex-6 - 12.x Software Known Issues related to the Virtex-6 FPGA

This answer record describes the Known Issues for the Virtex-6 FPGA generation used with ISE Design Suite 12.

The following represent a collection of issues that have been identified in the12.x ISE Design Tools and are related to Virtex-6 FPGA. There might be issues which are present and are not listed here. If you discover an issue that is not on this list, please open a WebCase with Xilinx Technical Support.

It is strongly recommended that designs be re-synthesized (and IP cores re-implemented) when re-implementing for production using the software that has production status speed files for the target device. This ensures that the changes to DRCs, timing models, clock topologies, and other fixes in softwareare picked up.

All ISE Design Suite 12.x:

BlockRAM/FIFO

(Xilinx Answer 42444) Design Advisory - Virtex-6 FPGA designs using 18K/36K block RAM or 18K FIFO must be re-run through timing analysis

MMCM

(Xilinx Answer 38132)Virtex-6 FPGA MMCM Design Advisory - MMCM BANDWIDTH attribute requirement
(Xilinx Answer 38133)Virtex-6 FPGA MMCM Design Advisory - Restriction for DIVCLK_DIVIDE value when Fclkin > 315 MHz

ISE Design Suite 12.3:

MMCM

(Xilinx Answer 39029) Virtex-6 MMCM - Incorrect phase shift from MMCM when using negative phase shifts
(Xilinx Answer 34219) Virtex-6 MMCM - Cascaded MMCMs may not work in hardware

ChipScope Pro/IBERT

(Xilinx Answer 37355) 12.2/12.3 ChipScope - IBERT - GTH - Parameter sweep is not supported
(Xilinx Answer 32912) 11.2 ChipScope Analyzer - "ERROR:INTERNAL_ERROR:Portability:basutencodeimp.c:229:1.24"
(Xilinx Answer 35420) 12.x/11.x ChipScope IBERT - Using LVDS_25 clock for system clock does not enable DIFF_TERM on input
(Xilinx Answer 33599) 11.x ChipScope Pro - "csejtag - The application failed to start because libCseCore.dll was not found. Re-installing the application may fix this problem."
(Xilinx Answer 37354) 12.2/12.3 ChipScope - IBERT - GTH - In the Analyzer the reset does not always set the error bit count to zero

MIG

(Xilinx Answer 38104) MIG v3.6, Virtex-6 DDR3 - The GUI does not allow AXI RDIMM data width selection
(Xilinx Answer 37997) MIG v3.6 Virtex-6 DDR3 Multi-Controller - GUI only allows single controller generation for CXT -1 devices
(Xilinx Answer 37863) MIG v3.6, Virtex-6 Multi-Controller - Default bank selection for all FF1760 packages results in MAP error

MAP

(Xilinx Answer 37835) 12.2 MAP - MMCM calibration circuit not included when global optimization is turned on

GTX Transceiver

(Xilinx Answer 35681) Virtex-6 GTX Transceiver - MMCM fails to lock and TX/RXRESETDONE fails to assert

PCI Express

(Xilinx Answer 37963) Virtex-6 FPGA Integrated Block Wrapper v2.1 for PCI Express - VHDL Wrapper Not Available for v2.1 Release

-----------------------------------------------------------------------------------------------------------------------------

ISE Design Suite12.2:

Block RAM

(Xilinx Answer 34859) Virtex-6 FPGA Block RAM Design Advisory - Address Space Overlap

Configuration

(Xilinx Answer 35451) iMPACT 12.x - Removing Numonyx J3 (Rev D, F) indirect programming support for Virtex-6 in 12.2

PlanAhead

(Xilinx Answer 35917) 12.1 Virtex-6 PlanAhead - When I import placement, BUFGDLL is not a supported primitive

ChipScope IBERT

(Xilinx Answer 36576) 12.2 ChipScope IBERT - When I do not select the Implement Design option no implementation scripts are created
(Xilinx Answer 34674) 11.x/12.1 ChipScope IBERT - Virtex-6 FPGA GTX: CORE Generator does not list upper GTXE1 quads of SX475T and LX550T
(Xilinx Answer 34683) 11.x/12.x ChipScope, Virtex-6 - IBERT parameter sweep tests show errors in the middle of the eye
(Xilinx Answer 36680) 12.2 CORE Generator - Generating an iBERT core fails with ERROR:sim - Unable to evaluate Tcl command

GTX Transceiver

(Xilinx Answer 37014) Virtex-6 GTX Transceiver: ERROR:MapLib:1226 - GTXE1 - DRC Error when POWER_SAVE is set incorrectly

XAUI

(Xilinx Answer 36228) LogiCORE IP XAUI v9.1 and v9.1 rev1 - Virtex-6 GTX_POWER_SAVE needs to be updated to target ISE 12.2

Embedded Tri-mode Ethernet MAC Wrapper v1.4

(Xilinx Answer 36223) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper v1.4 - When targeting SGMII or 1000BASE-X, DRC error is seen regarding GTX POWER_SAVE

Ethernet 1000BASE-X PCS/PMA or SGMII v10.5

(Xilinx Answer 36957) LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v10.5 - GMII setup/hold errors seen when targeting Virtex-6 HXT

MPMC

(Xilinx Answer 33817) 12.2 EDK, MPMC v6.00.a, Virtex-6 - ERROR:ConstraintSystem:58 - Constraint does not match any design objects

-----------------------------------------------------------------------------------------------------------------------------

ISE Design Suite12.1:

Aurora 64B/66B

(Xilinx Answer 35371) Aurora 64B/66B v4.1 - Release Notes and Known Issues for ISE Design Suite 12.1

Block RAM

(Xilinx Answer 34859) Virtex-6 FPGA Block RAM Design Advisory - Address Space Overlap

MMCM

(Xilinx Answer 36274) 11.5, 12.1 Virtex-6 MMCM - MMCM does not lock after device startup andMMCM reset

I/O

(Xilinx Answer 36082) Virtex-6 SelectIO - DCI Cascade across non-continuous banks is supported in ISE software 12.2
(Xilinx Answer 36320) Virtex-6 - N-side pseudo-differential output driven by OSERDES does not toggle
(Xilinx Answer 35952) Config BitGen - UnusedPin option not pulling up unused I/Os in Virtex-6 devices

MAP/PAR

(Xilinx Answer 35574) 12.1 Project Navigator - The -mt (Enable Multi-Threading) option is greyed out in MAP and PAR Process Properties

Timing Simulation

(Xilinx Answer 35514) 12.1 - Timing simulation issue when targeting Virtex-6 devices

iMPACT

(Xilinx Answer 33942) 11.x iMPACT - When I add a Winbond SPI Flash for Indirect programming, I am prompted for a Data Width. Does Virtex-6 FPGA support x2 or x4 SPI?

Partial Reconfiguration

(Xilinx Answer 35399) 12.1 Virtex-6 FPGA Partial Reconfiguration - RAM contents not written correctly to Partial Bitfiles

ChipScope

(Xilinx Answer 35417) 12.1 ChipScope Pro - Virtex-6Q, Spartan-6Q, and Spartan-6Q LX/LXT devices are not supported in ChipScope Pro tools
(Xilinx Answer 33701) 12.1/11.x ChipScope Pro - IBERT - Virtex-6 - IBERT generation fails on Virtex-6 when I enable 8 or more GTs
(Xilinx Answer 34674) 11.x/12.x ChipScope, IBERT -Virtex-6 GTX, CORE Generator does not list upper GTXE1 quads of SX475T and LX550T
(Xilinx Answer 34683)11.x/12.x ChipScope, Virtex-6 - IBERT parameter sweep tests show errors in the middle of the eye

GTX Transceiver Wizard

(Xilinx Answer 34191) Virtex-6 FPGA GTX Transceiver Wizard - Attribute updates for production silicon

GTX Transceiver

(Xilinx Answer 35055) Virtex-6 FPGA GTX Transceiver - Automatic macro insertion for unused GTX Transceivers

MPMC

(Xilinx Answer 34717) 12.1 EDK, MPMC v6.00.a- ERROR:EDK:1558 - PORT MPMC_Clk_Wr_I0 not found in mpd

MIG

(Xilinx Answer 35742) MIG v3.0-3.4 Virtex-6 DDR2 SDRAM - Incorrect timing on DDR2_RAS_N
(Xilinx Answer 35247) MIG v3.4 Virtex-6 DDR2/DDR3 - Fixed Pin-Out tool does not allow selection of VREF sites
(Xilinx Answer 35252) MIG v3.0-3.4 Virtex-6 DDR3 - REFCLK Frequency (IODELAYCTRL Reference clock) must be 300 MHz for interfaces running between 480-533 MHz
(Xilinx Answer 36503) MIG v3.4 Virtex-6 DDR3 - Cannot see phy_init_done go high in simulation

PCI Express

(Xilinx Answer 33834) Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - Use of Component Name "core" Causes Implementation Failures using VHDL Flow
(Xilinx Answer 34009) Virtex-6 FPGA ML605 Board- PCI Express Link Will Not Train; Implementations for PCI Express Must Use the v1.3 Integrated Block Wrapper for PCI Express
(Xilinx Answer 34115) Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - WARNING:Xst:2016 - Found a loop when searching source

Tri-mode Ethernet MAC v1.4

(Xilinx Answer 33195) Virtex-6 FPGA Embedded Tri-mode Ethernet MAC Wrapper - Adjusting IDELAYs to meet GMII and RGMII setup and hold requirements

Revision History

09/24/2012 - Minor update; no change to content
07/18/2011 - Updated to include BRAM/FIFO issue
10/22/2010 - Added MMCM (Xilinx Answer 34219)
10/08/2010 - Updated for 12.3
08/02/2010 - Updated for 12.2 and added answer records for 12.1
05/04/2010 - Added GTX Transceiver (Xilinx Answer 35055) and Timing Simulation (Xilinx Answer 35514)
05/03/2010 - Initial 12.1 release


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