Xilinx PlanAhead 工具解决方案中心
PlanAhead 工具解决方案中心可用于解决与 PlanAhead 工具相关的所有问题。无论您想了解如何使用工具还是想调试问题，请使用 PlanAhead 工具解决方案中心来指导您获取正确的信息。
设计助手
Xilinx PlanAhead Tool Solution Center - Design Assistant
ThePlanAhead Tool Design Assistant will walk you through the different flows available in the PlanAhead tool while debugging commonly encountered issues such as floorplanning and pin placement failures. The Design Assistant will not only provide useful design and troubleshoot information but also point you to the exact documentation you need to read to help you use the PlanAhead tool efficiently.NOTE:This answer record is part of the Xilinx PlanAhead Tool Solution Center(Xilinx Answer 37100). The Xilinx PlanAhead Tool Solution Center is available to address all questions related to the PlanAhead tool. Whether you are starting a new design with the PlanAhead tool or troubleshooting a problem, use the PlanAhead Tool Solution Center to guide you to the right information.
First, select the topic for which you have a question or are troubleshooting an issue related to your PlanAhead tool design. This will ensure the PlanAhead Tool Design Assistant points you to the information you need to continually move forward with your design.
(Xilinx Answer 37380) - Functionality and Usage
(Xilinx Answer 37381) - Features
(Xilinx Answer 37379) - Error/Warning Codes
(Xilinx Answer 37382) - Quality of Results
技术文档
Xilinx PlanAhead 工具解决方案中心 - 文档
使用 PlanAhead 工具时，敬请参考以下文档。
注：本答复记录是 Xilinx PlanAhead 工具解决方案中心的一部分(Xilinx 答复 37100)。Xilinx PlanAhead 工具解决方案中心可用于解决与 PlanAhead 工具相关的所有问题。无论您是要使用 PlanAhead 工具来进行新设计还是要调试问题，请使用 PlanAhead 工具解决方案中心来指导您获取相应的信息。
12.1 PlanAhead 综合资源
12.1 PlanAhead 教程
- 快速 Front-to-Back 简介 - UG673
- 设计分析和布局规划 - UG676
- I/O 引脚规划 - UG674
- 使用 CORE Generator 进行 RTL 设计和 IP 生成 - UG675
- 使用 Chipscope 进行调试 - UG677
- 利用设计保存功能实现可预测结果 - UG747
设计咨询
PlanAhead 解决方案中心 - 设计咨询
针对一般设计过程出现的重大问题创建设计咨询答复记录，精选后用于 Xilinx 提醒通知系统。注: 本答复记录是 Xilinx PlanAhead 解决方案中心(Xilinx 答复 37100)的一部分。Xilinx PlanAhead 解决方案中心可解决所有与 PlanAhead 相关的问题。无论您是要使用 PlanAhead 来进行新设计还是要调试问题，请使用 PlanAhead 解决方案中心来指导您获取相应的信息。
设计咨询
3/19/2011 - (Xilinx 答复 41128)- 13.1 PlanAhead - 导入 ISE Project 为 NGDBUILD 设置 -r (忽略位置约束) 选项 。
修订历史
3/19/2011 - 添加 AR 41128
常见问题
Xilinx PlanAhead Tool Solution Center - Top Issues
The following answer records cover current known issues as well as commonly asked questions related to the PlanAhead tool.
NOTE: This answer record is part of the Xilinx PlanAhead Tool Solution Center (Xilinx Answer 37100). The Xilinx PlanAhead Tool Solution Center is available to address all questions related to the PlanAhead tool. Whether you are starting a new design with the PlanAhead tool or troubleshooting a problem, use the PlanAhead Tool Solution Center to guide you to the right information.
Known Issues
(Xilinx Answer 34799) 12.1 PlanAhead Known Issues
(Xilinx Answer 36167) 12.2 PlanAhead Release Notes
Top Issues
(Xilinx Answer 34878) 12.1 PlanAhead - "ERROR: [HD-UCFReader 1] Unrecognized symbol \/leaf_2\/cont_ram\/v16384x72/BU2132"
(Xilinx Answer 35743) 12.1 PlanAhead - Incorrect BIVB DRC errors from PlanAhead
(Xilinx Answer 34793) 12.1 PlanAhead - Synthesis with a netlist as top level in an RTL Project
(Xilinx Answer 34858) 12.1 PlanAhead - Error on constraints when running Implementation in PlanAhead points to merged .ucf
(Xilinx Answer 34876) 12.1 PlanAhead - "RTL I/O Planner view" errors on LOC constraints