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Xilinx Zynq UltraScale+ MPSoC Solution Center

The Zynq UltraScale+ MPSoC Solution Center is available to address all questions related to the Zynq UltraScale+ MPSoC.

Whether you are starting a new design with Zynq UltraScale+ MPSoC or troubleshooting a problem, use the Zynq UltraScale+ MPSoC solution center to guide you to the right information.

QUICK LINKS:

Product Page

UltraScale Architecture and Product Overview

设计助手

Zynq UltraScale+ MPSoC - Processing System (PS) DDR Controller

This answer record helps you find all Zynq UltraScale+ MPSoC solutions related to the Processing System (PS) DDR Controller known issues.

Note: This answer record is part of Xilinx Zynq UltraScale+ MPSoC Solution Center (Xilinx Answer 64375).

The Xilinx Zynq UltraScale+ MPSoC Solution Center is available to address all questions related to Zynq UltraScale+ MPSoC.

Whether you are starting a new design or troubleshooting a problem, use the Zynq UltraScale+ MPSoC Solution Center to guide you to the right information.


General Guidance/Documentation

Xilinx Answer
Title
(Xilinx Answer 66193)
What are the limitations of the PS DDR controller? Which device should I choose?
(Xilinx Answer 67330)PS DDR Pin Swap Guidelines

Known issues

Xilinx AnswerTitleTool Version FoundTool Version Resolved (Planned)
(Xilinx Answer 65982)Zynq UltraScale+ MPSoC, Vivado 2015.4 - Patch for PS DDR3/DDR4/LPDDR4 and GTR transceiver support2015.4(2016.1)
(Xilinx Answer 66571)Processor System IP GUI Limitations with PS DDR topologies2015.4(2016.1)

设计咨询

Zynq UltraScale+ MPSoC 器件的设计咨询主答复记录

Zynq 数据表、技术参考手册和其他文档均包含 Zynq UltraScale+ MPSoC 器件。

此处列举了重要的设计咨询和其他超出这些文档范围的重要事项。

技术内容源于 Xilinx Zynq UltraScale+ MPSoC 解决方案中心 (Xilinx 答复 64375)


2018 年 8 月 6 日发布的设计咨询提醒

(Xilinx Answer 71293)Zynq UltraScale+ MPSoC 的设计咨询:2017.x FSBL 根据分区报头的内容在分区上执行安全操作。 [SECURITY]
(Xilinx Answer 71326)  Zynq UltraScale+ MPSoC 的设计咨询:2017.x、2018.1 或 2018.2 的 FSBL 不检查所有 RSA_EN eFUSE [SECURITY]


2017 年 3 月 19 日发布的设计咨询提醒:

(Xilinx Answer 70622)Zynq UltraScale+ MPSoC 的设计咨询:2017.x Xilinx 开发工具和软件在多个分区中重复使用相同的 AES 密钥和 IV 对。 [SECURITY]


2017 年 4 月 17 日发布的设计咨询提醒:

(Xilinx 答复 69034)7 系列、UltraScale 和 UltraScale+ 的设计咨询,Vivado 2016.3 之前的所有版本都没有包括差分 I/O 标准的飞行时间延迟。
(Xilinx Answer 68615)Zynq UltraScale+ MPSoC 的设计咨询:如果第一个参数页面有数据损坏,从 NAND 启动可能就会失败。

2017 年 4 月 10 日发布的设计咨询提醒:

(Xilinx 答复 68832)采用 Vivado 2016.4(或更早版本)进行 UltraScale FPGA、UltraScale+ FPGA 以及 Zynq UltraScale+ MPSoC eFUSE 编程的设计咨询 [SECURITY]

2016 年 12 月 5 日发布的设计咨询提醒

(Xilinx 答复 68210)FSBL 在外部 DDR 中验证引导镜像 [SECURITY]

设计咨询提醒: 2016.10.17

(Xilinx 答复 67861)如何从 Vivado 2016.2 或更早的版本更新

 

设计咨询提醒: 2016.4.18

(Xilinx 答复 66944)面向 Zynq UltraScale+ MPSoC 和 Kintex UltraScale+ FPGA 的设计咨询- 更新的封装引脚

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