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AR# 64761

Bitstream Loading across the PCI Express Link in UltraScale Devices for Tandem PCIe and Partial Reconfiguration

描述

This answer record provides a PDF document describing bitstream loading across the PCI Express Link for Tandem PCIe or Partial Reconfiguration solutions.

The associated files have also been provided in a ZIP file.

The provided mechanism to load bitstreams is applicable for UltraScale Architecture Gen3 Integrated Block for PCI Express cores. 

This mechanism will allow users to deliver via MCAP Tandem Stage 2 bitstreams, clearing bitstreams, and partial bitstreams for Tandem Configuration and/or Partial Reconfiguration designs.

For tandem PCIe second stage bitstream loading across the PCI Express Link on 7 Series devices, please refer to (Xilinx Answer 51950).

解决方案

Please download the "Bitstream Loading across the PCI Express Link in UltraScale Devices for Tandem PCIe and Partial Reconfiguration"  PDF and the associated design files at the end of this answer record.

The file names are:

  • Xilinx_Answer_64761_UltraScale_Devices.pdf
  • Xilinx_Answer_64761_Files.zip

Revision History:

06/30/2015 - Initial release
10/06/2015 - Updated for 'Tandem Field Update'

附件

文件名 文件大小 File Type
Xilinx_Answer_64761_Files.zip 6 MB ZIP
Xilinx_Answer_64761__UltraScale_Devices.pdf 2 MB PDF
AR# 64761
日期 11/10/2015
状态 Active
Type 综合文章
IP
  • UltraScale FPGA Gen3 Integrated Block for PCI Express (PCIe)
的页面