过去7天的问答
AR #22532 - 9.1i PrimeTime - Known issues for Virtex-II Pro Customer flow in 8.1i and 9.1i
最后更新日期: 2008-08-28 00:00:00.0
AR #30279 - 10.1 EDK SP2, plbv46_pci_v1_02_a - The latest Tactical Patch "plbv46_pci_v1_03_a" fixes issues related to Linux booting on Ml510 system, qvirtex4, qrvirtex4 support and various other issues
最后更新日期: 2008-08-28 00:00:00.0
AR #30029 - LogiCORE FIFO Generator v4.2 - Setup/Hold time violations occur in the Unconstrained Path Report
最后更新日期: 2008-08-28 00:00:00.0
AR #18329 - LogiCORE Endpoint for PCI Express - What clock frequency can be used to clock a Xilinx LogiCORE Endpoint for PCI Express design for the Virtex-5, Virtex-4, or Virtex-II Pro devices?
最后更新日期: 2008-08-27 00:00:00.0
AR #23990 - 8.2i MAP - Master Answer Record for MAP Trimming Issues
最后更新日期: 2008-08-27 00:00:00.0
AR #30112 - 10.1 MAP - Net SAVE property behavior has changed and might lead to DRC failures
最后更新日期: 2008-08-27 00:00:00.0
AR #31408 - Xilinx Application Note 716 - Where can I find the various files for the application note (filetree.tgz and others)?
最后更新日期: 2008-08-27 00:00:00.0
AR #31574 - 10.1 Virtex-5 MAP - ERROR:PhysDesignRules:1577 - Illegal routing. The DCM_ADV block ...
最后更新日期: 2008-08-27 00:00:00.0
AR #24835 - VCS/NCSIM - "Warning-[SIOB] Select index out of bounds"
最后更新日期: 2008-08-26 00:00:00.0
AR #30704 - 10.1 Install - EDK Service Pack Release Notes (README)
最后更新日期: 2008-08-26 00:00:00.0
AR #31168 - 10.1.01 ISE - View HDL instantiation Template results in ERROR:HDLParsers:3264 - Can't read file "/../..clock_source2.vhd" (...)
最后更新日期: 2008-08-26 00:00:00.0
AR #31307 - 10.1 ChipScope Pro - ERROR:sim - Error: XST failed for chipscope_ila_v1_02_a. ERROR:Xst:1312 - Loop has iterated 64 times. Use "set -loop_iteration_limit XX" to iterate more
最后更新日期: 2008-08-26 00:00:00.0
AR #31441 - 10.1 EDK - Why does the lwIP library always assume that I will be using my first PHY?
最后更新日期: 2008-08-26 00:00:00.0
AR #31563 - 10.1 EDK - When I generate a VxWorks BSP for the Power PC 440, not all of the necessary files are copied into the BSP directory
最后更新日期: 2008-08-26 00:00:00.0
AR #31562 - 10.1 EDK - When using an SDMA PIM with MPMC in a Power PC 440 system, the LLDMA driver still uses DCR access to configure the SDMA
最后更新日期: 2008-08-26 00:00:00.0
AR #31565 - 10.1 EDK - XMD gives a segmentation fault
最后更新日期: 2008-08-26 00:00:00.0
AR #12582 - Spartan-3 Family, Virtex-II, DCM - Is it possible for CLKDV and CLKFX to be phase-aligned with the same rising edge of CLK0?
最后更新日期: 2008-08-25 00:00:00.0
AR #30056 - LogiCORE FIFO Generator v4.3 - Release Notes and Known Issues for 10.1 IP Update 0 (10.1_IP0)
最后更新日期: 2008-08-25 00:00:00.0
AR #30143 - LogiCORE XAUI v7.3 - Release Notes and Known Issues for ISE 10.1 Initial IP Update (IP_10.1.0)
最后更新日期: 2008-08-25 00:00:00.0
AR #31379 - LogiCORE FIFO Generator v4.3 - Cannot change read/write clock frequencies with Built-in FIFO when importing an XCO file
最后更新日期: 2008-08-25 00:00:00.0
AR #20816 - Virtex-4 RocketIO - Should unused MGTs be powered and/or filtered?
最后更新日期: 2008-08-22 00:00:00.0
AR #29227 - 9.2i MAP - "INTERNAL_ERROR:Pack:pki3aiomend.c:419:1.11 - Expected a valid output signal for block"
最后更新日期: 2008-08-22 00:00:00.0
AR #30174 - LogiCORE Interleaver/De-Interleaver - Release Notes and Known Issues
最后更新日期: 2008-08-22 00:00:00.0
AR #29253 - LogiCORE Interleaver/De-Interleaver v5.0 Patch - Release Notes/README for Hardware Timeout Issue
最后更新日期: 2008-08-22 00:00:00.0
AR #31508 - Virtex-5 GTP RocketIO - TXKERR and TXRUNDISP meaning for a 2-byte interface
最后更新日期: 2008-08-22 00:00:00.0
AR #31509 - Virtex-5 GTX RocketIO - TXKERR and TXRUNDISP meaning for a 4-byte interface
最后更新日期: 2008-08-22 00:00:00.0
AR #31501 - MIG v2.2, Virtex-4 RLDRAM II - Removal of configuration register support
最后更新日期: 2008-08-22 00:00:00.0
AR #31535 - XtremeDSP Development Kit - Why does the NT302-0000_Spartan_to_Virtex_Interface Application Note use the vidime.c functions rather than those in the FUSE C++ API documentation?
最后更新日期: 2008-08-22 00:00:00.0