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UltraScale and UltraScale+ GTY Transceivers

Getting StartedDesign ResourcesSupport ResourcesTransceiver IP Resources

Refer to the High Speed Serial Product Page for more information on Xilinx GTY Transceivers.

High-Speed Serial I/O Designer's GuideDate
 Basic Concepts 
 Purpose of SERDES 
 History of SERDES 
 Alignment, Encoding, Emphasis, Buffers, Channel Bonding and Clock Correction 
UltraScale GTY Transceivers User GuideDate
 RX Byte and Word Alignment09/20/2017
 RX 8B/10B Decoder09/20/2017
 Buffer Control09/20/2017
 RX Clock Correction09/20/2017
 RX Channel Bonding09/20/2017
 RX Synchronous Gearbox09/20/2017
 RX Clock Data Recovery (CDR)09/20/2017

Product Specifications

Product Specifications

UltraScale Transceiver Wizard

UltraScale Transceiver Wizard

Refer to the UltraScale FPGAs Transceivers Wizard IP Product Page for more information regarding this IP.

Using the Wizard IP CoreDate
 Overview04/04/2018
 Designing with the Core04/04/2018
 Design Flow Steps04/04/2018
 Example Design04/04/2018
 Test Bench Usage04/04/2018
 UltraScale Transceiver Wizard - Release Notes and Known Issues04/09/2018

Understanding GT Transceiver Features

Understanding GT Transceiver Features

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