Implementing SMPTE SDI Interfaces with UltraScale GTH Transceivers Application Note (XAPP1248)

Document ID: XAPP1248
Release Date: 2023-11-08
Revision: v1.6 English

Summary
Introduction
Features
Using UltraScale GTH Transceivers for SDI Interfaces
GTH Transceiver Reference Clocks
Resets
GTH TX Resets
GTH RX Resets
GTH PLL Use Models for SDI Applications
Use Model 1: A Single Transceiver Active in the Quad, RX and TX are Dynamically Clocked by QPLL0 and QPLL1
Use Model 2: A Single Transceiver Active in the Quad, RX Clocked by the QPLL1, TX Clocked by the QPLL0
Use Model 3: Multiple Transceivers Active in the Quad, All RX and TX are Dynamically Clocked by QPLL0 and QPLL1
Use Model 4: Multiple Transceivers are Active in a Quad, All RX Use the QPLL1, All TX Use the QPLL0
Use Model 5: A Single Transceiver Active in the Quad, RX Is Clocked by QPLL1 and TX Is Dynamically Clocked by QPLL1 and CPLL
SDI Electrical Interface
SD-SDI Considerations
Receiving SD-SDI
Transmitting SD-SDI
Generating an SD-SDI Recovered Clock
Automatic RX SDI Mode Detection
RX Bit Rate Detection
Implementing an SDI Interface in an UltraScale Device
Generating the GTH Wizard IP
Generating the SMPTE UHD-SDI IP Core
Instantiating the UHD-SDI Wrappers
SDI Wrapper Port List
SDI Wrapper Parameter List
Video Transport Detector Ports
SD-SDI RX EDH Processor
GTH Initialization and Reset and Change Sequence Failure Codes
SDI Timing Constraints
Example SDI Demonstrations
SDI Demonstration
Configuring FPGA with Precompiled Bit File
Demo Status LED
Reference Design
Setup
Running the Reference Design
Compiling SDI Demonstration
inrevium 12G-SDI FMC Card Controller
Recompiling FMC Controller Vitis Project
FPGA Resource Usage
Conclusion
Glossary
References
Revision History
Please Read: Important Legal Notices

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