ISE 10

The clock correction (CC) module is a design that connects to the Virtex®-5 FPGA RocketIO™ GTX transceiver. The design implements clock tolerance compensation using an elastic buffer in FPGA logic. This module must be used when clock tolerance compensation is required and the clock correction sequence is one byte.

This is a test.

This Known Issues document is a supplement to the Release Notes and Installation Guide and contains links to Answer Records that contain information on known issues in the ISE® Design Suite.

To inform you of changes in relation to part numbers used to order Xilinx® ISE® Design Suite software and fee-based LogiCORE™ IP cores.

本技术文档介绍了 ISE® 设计套件 10.1 内跟 Virtex®-5 FXT FPGA 特性相关的已知问题。