RXAUI

The RXAUI Getting Started Guide provides information about generating a LogiCORE™ IP RXAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The RXAUI User Guide provides information about generating a LogiCORE™ IP RXAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.

The LogiCORE™ IP RXAUI core is a high-performance, low pin count 10-Gbps interface intended to allow physical separation between the data-link layer and physical layer devices in a 10-Gigabit Ethernet system. The RXAUI core implements a single-speed full-duplex 10-Gbps Ethernet Reduced Pin eXtended Attachment Unit Interface (RXAUI) solution for Xilinx Virtex®-6 FPGAs that complies with the Dune Networks RXAUI specification.