The XAUI v8.1 User Guide provides information about generating a LogiCORE™ IP XAUI core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx® tools.
The LogiCORE™ IP XAUI core is a high-performance,
low pin count 10-Gbps interface intended to allow
physical separation between data-link layer and physical
layer devices in a 10-Gigabit Ethernet system.
The LogiCORE™ IP XAUI Getting Started Guide provides instructions for generating the core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx® tools.